Logic synthesis tools synthesize circuit structures to optimize specific targets given
reasonable constraints and runtime using a set of well-defined operators. The efficiency of …

The efficiency issue of logic optimization becomes critical as the scale of VLSI designs
grows. Since various algorithms are interleaved during optimization to ensure quality, it is …

An Open-Source EDA Flow for Asynchronous Logic Page 1 27 2168-2356/21©2021 IEEE
Copublished by the IEEE CEDA, IEEE CASS, IEEE SSCS, and TTTC March/April 2021 Editor’s …

Logic rewriting is an important part in logic optimization. It rewrites a circuit by replacing local
subgraphs with logically equivalent ones, so that the area and the delay of the circuit can be …

Logic rewriting is an effective but time-consuming technique to optimize the multilevel logic
network by rewriting subnetworks of the input network with other logic equivalent structures …

Implementing dedicated machine learning hardware is becoming essential in many
circumstances, raising the challenge for integrated circuit designers to reach resource …

Lookup-table (LUT) mapping is an indispensable step in FPGA design flows, and also
serves as a building block in many technology-independent optimization algorithms …

Deep neural networks tend to be extensively power and area consuming for their processing
hardware. Integrated circuit designers face a considerable challenge when implementing …

With the development of large-scale integrated circuits, electronic design automation~(EDA)
tools are increasingly emphasizing efficiency, with parallel algorithms becoming a trend. The …

Abstract Modern Electronic Design Automation (EDA) is complex and computationally
challenging. It consists of a series of difficult optimization problems, accompanied by various …