A subharmonically injection-locked PLL with calibrated injection pulsewidth
CL Wei, TK Kuan, SI Liu - … on Circuits and Systems II: Express …, 2015 - ieeexplore.ieee.org
A subharmonically injection-locked phase-locked loop (SIPLL) using a pulsewidth-
calibrated loop is presented. The injection timing and the pulsewidth of the injected pulse …
calibrated loop is presented. The injection timing and the pulsewidth of the injected pulse …
[HTML][HTML] 應用於雙速率串列傳輸系統之時脈與資料回復電路
KW Lu - 2013 - ir.lib.ncu.edu.tw
摘要(中) 隨半導體產業發展與電腦相關產業的興起, 資料傳輸頻寬逐漸上升,
傳統並列傳輸方式漸漸被串列傳輸取代, 例如DisplayPort, SATA, USB, 及PCI-E …
傳統並列傳輸方式漸漸被串列傳輸取代, 例如DisplayPort, SATA, USB, 及PCI-E …
[PDF][PDF] 基于PDSOI 工艺的抗SET 锁相环设计
吕荫学， 刘梦新， 罗家俊， 叶甜春 - 微电子学与计算机, 2013 - journalmc.com
基于0.35 μm PDSOI 工艺设计了一款输出频率范围为700M Hz-1.0 GHz 的锁相环电路,
利用Sentaurus TCAD 工具对其进行单粒子瞬变(SET) 混合模拟仿真, 确定其SET …
利用Sentaurus TCAD 工具对其进行单粒子瞬变(SET) 混合模拟仿真, 确定其SET …
A Low Jitter Self-Calibration PLL for 10-Gbps SoC Transmission Links Application
KH Cheng, YC Tsai, CNJ Liu, KW Hong… - IEICE transactions on …, 2009 - search.ieice.org
A 2.5 GHz 8-phase phase-locked loop (PLL) is proposed for 10-Gbps system on chip (SoC)
transmission links application. The proposed PLL has several features which use new …
transmission links application. The proposed PLL has several features which use new …
A BiCMOS upconverter with 1.9 GHz multiband frequency synthesizer for DVB-RCT application
E de Foucauld, G Billiot… - Proceedings of the Bipolar …, 2005 - ieeexplore.ieee.org
In this paper, we present an integrated upconversion stage including an integer-N
synthesizer in a 0.35/spl mu/m BiCMOS process. This chip is, to our knowledge, the first …
synthesizer in a 0.35/spl mu/m BiCMOS process. This chip is, to our knowledge, the first …
802.11 a CMOS 頻率合成器設計
潘宏良， 溫瓌岸 - 2003 - ir.lib.nycu.edu.tw
現今熱門的射頻電路有無數學者在研究, 瀏覽各式的論文雖然已成功地在CMOS 製程下將VCO
特性設計得符合無線網路的規格, 但射頻電路容易受干擾的特性若要成功地整合有數位電路的 …
特性設計得符合無線網路的規格, 但射頻電路容易受干擾的特性若要成功地整合有數位電路的 …
[PDF][PDF] Adaptable MOS current mode logic for multi-band frequency synthesizers
M Houlgate - 2005 - repository.library.carleton.ca
A new form of MOS Current Mode Logic (MCML) is introduced which allows the drive current
and voltage swing of the logic gates to be adaptively controlled, enabling real-time …
and voltage swing of the logic gates to be adaptively controlled, enabling real-time …
A Single-Event Hardened Phase-Locked Loop Design Based on PDSOI CMOS Process
Y LV, M LIU, J LUO, T YE - Microelectronics & Computer, 2013 - journalmc.com
Based on the 0.35 μm PDSOI CMOS process, a normal phase-locked loop with a frequency
range of 700 M Hz to 1.0 GHz is designed. By using Sentaurus TCAD, the radiation …
range of 700 M Hz to 1.0 GHz is designed. By using Sentaurus TCAD, the radiation …
A regulated supply tunning voltage-controlled oscillator with built-in test and calibration
W San-Um, T Masayoshi - ECTI-CON2010: The 2010 ECTI …, 2010 - ieeexplore.ieee.org
This paper presents a regulated supply tuning voltage-controlled oscillator with built-in test
and calibration. A low-dropout regulator with an integrated low-pass filter operates as a …
and calibration. A low-dropout regulator with an integrated low-pass filter operates as a …