Design of a two-bit magnitude comparator based on pass transistor, transmission gate and conventional static CMOS logic

S Lubaba, KM Faisal, MS Islam… - 2020 11th International …, 2020 - ieeexplore.ieee.org
Since there is a swift technological progress going on in the recent years, semiconductor
industry evolved to such an extend that requirement of optimal performance in electronic …

Low power design of a two bit mangitude comparator for high speed operation

M Hasan, UK Saha, MS Hossain… - 2019 International …, 2019 - ieeexplore.ieee.org
Binary magnitude comparator is considered as an elementary apparatus in Arithmetic Logic
Unit. Due to increased use of portable devices nowadays, energy efficient designs having …

Design and simulation of a small power two-bit mc circuit via full adder logic

S Bhattacharjee, A Vyakaranam, DS Svpk… - Journal of physics …, 2021 - iopscience.iop.org
Abstract In Very Large-Scale Integration (VLSI) systems, a magnitude comparator (MC) is a
component of Arithmetic Logic Unit (ALU) used to make binary decisions. Recent …

Two-Bit Magnitude Comparator Design Using Gate Diffusion Input Technique and Static CMOS Logic

UB Joy, A Chakraborty, P Biswas, A Das… - … Electrical and Signal …, 2023 - ieeexplore.ieee.org
Magnitude comparison is an elementary operation of Arithmetic Logic Unit (ALU) of modern
processors. Due rapid increased use of portable devices, circuit designs having optimal …

HYBRID AND DIRECT LOGIC FULL ADDER BASED COMPARATOR USING MICROWIND

M Bhavani, K Vasanthi, KK Rani… - International Journal of …, 2022 - search.proquest.com
One of the basic elements of ALU is Magnitude Comparator. Here in this paper, the design
of Magnitude Comparator is described by using different styles of Full Adder design logic …