New structure transistors for advanced technology node CMOS ICs

Q Zhang, Y Zhang, Y Luo, H Yin - National Science Review, 2024 - academic.oup.com
Over recent decades, advancements in complementary metal-oxide-semiconductor
integrated circuits (ICs) have mainly relied on structural innovations in transistors. From …

Optimization of design space for vertically stacked junctionless nanosheet FET for analog/RF applications

S Valasa, S Tayal, LR Thoutam - Silicon, 2022 - Springer
This paper investigates the various device dimensions such as gate length (Lg), nanosheet
thickness (TNS), and nanosheet width to optimize the design space for vertically stacked …

Layout optimization of complementary FET 6T-SRAM cell based on a universal methodology using sensitivity with respect to parasitic-and-values

Y Luo, L Cao, Q Zhang, Y Cao, Z Zhang… - … on Electron Devices, 2022 - ieeexplore.ieee.org
Complementary FET (CFET) is a promising booster for further area reductions in static
random-access memory (SRAM) cells. However, the performance degrading by a series of …

Novel channel-first fishbone FETs with symmetrical threshold voltages and balanced driving currents using single work function metal process

L Cao, Q Zhang, Y Luo, J Gu, W Gan… - … on Electron Devices, 2022 - ieeexplore.ieee.org
In this article, one feasible fabrication approach for novel fishbone FETs using the channel-
first and single work function metal (sWFM) processes is proposed and investigated by 3-D …

CMOS Scaling for the 5 nm Node and Beyond: Device, Process and Technology

HH Radamson, Y Miao, Z Zhou, Z Wu, Z Kong, J Gao… - Nanomaterials, 2024 - mdpi.com
After more than five decades, Moore's Law for transistors is approaching the end of the
international technology roadmap of semiconductors (ITRS). The fate of complementary …

Investigation of novel hybrid channel complementary FET scaling beyond 3-nm node from device to circuit

Y Luo, Q Zhang, L Cao, W Gan, H Xu… - … on Electron Devices, 2022 - ieeexplore.ieee.org
Complementary FET (CFET) is a promising candidate for CMOS scaling beyond 3-nm
technology node. In this article, a novel hybrid channel CFET (HC-CFET) is proposed, which …

[HTML][HTML] Study of Selective Dry Etching Effects of 15-Cycle Si0.7Ge0.3/Si Multilayer Structure in Gate-All-Around Transistor Process

E Liu, J Li, N Zhou, R Chen, H Shao, J Gao, Q Zhang… - Nanomaterials, 2023 - mdpi.com
Gate-all-around (GAA) structures are important for future logic devices and 3D-DRAM. Inner-
spacer cavity etching and channel release both require selective etching of Si0. 7Ge0. 3 …

[HTML][HTML] A Novel Si Nanosheet Channel Release Process for the Fabrication of Gate-All-Around Transistors and Its Mechanism Investigation

X Sun, D Wang, L Qian, T Liu, J Yang, K Chen, L Wang… - Nanomaterials, 2023 - mdpi.com
The effect of the source/drain compressive stress on the mechanical stability of stacked Si
nanosheets (NS) during the process of channel release has been investigated. The stress of …

Investigation of fabricated CMOS fishboneFETs and treeFETs with strained SiGe nano-fins on bulk-Si substrate

L Cao, Q Zhang, J Yao, J Li, Y Liu, Y Luo… - IEEE Electron …, 2023 - ieeexplore.ieee.org
Based on the bulk-Si substrate, the CMOS tree-like FETs including the FishboneFETs with
bottom SiGe nano-fin and the TreeFETs without bottom SiGe nano-fin were both designed …

Impact of Gate Length and Doping Variation on the DC and Analog/RF Performance of sub - 3nm Stacked Si Gate-All-Around Nanosheet FET

N Yadav, S Jadav, G Saini - Silicon, 2023 - Springer
Abstract The nanosheet Field Effect Transistors (FETs) are the promising device architecture
for sub-5 nm technology node as per the International Roadmap for Devices and Systems …