BS Louie, JW Han, Y Widjaja - US Patent 11,100,994, 2021 - Google Patents
A content addressable memory cell includes a first floating body transistor and a second floating body transistor. The first floating body transistor and the second floating body …
M Pasotti, L Davide, F De Santis - US Patent 8,693,256, 2014 - Google Patents
(57) ABSTRACT A non-volatile memory device integrated in a chip of semi conductor material. An embodiment of a memory device includes a plurality of memory cells. Each …
BS Louie, JW Han, Y Widjaja - US Patent 11,594,280, 2023 - Google Patents
G11C15/00—Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of …
A non-volatile memory includes cells arranged in rows and columns. Each memory cell includes an access portion and a control portion. The access and control portions share an …
A Pagani, FG Ziglioli - US Patent 9,318,313, 2016 - Google Patents
BACKGROUND As is known, the production of integrated devices envis ages testing steps that allow to check proper operation of the components obtained. Tests of this kind, such as …
N Ueda, S Katoh - US Patent 9,312,264, 2016 - Google Patents
The present invention provides a non-volatile memory device using a memory transistor including an oxide semiconductor, capable of writing with low power consumption, without …
Q Tang, X Guo, R Ghodsi - US Patent 10,515,692, 2019 - Google Patents
Methods of operating a memory device applying a program ming pulse having a plurality of different voltage levels to an access line coupled to a plurality of memory cells, enabling a …
M Pasotti, M Carissimi, L Davide - US Patent 8,619,469, 2013 - Google Patents
An embodiment of a non-volatile memory device integrated in a chip of semiconductor material is proposed. The memory device includes a plurality of memory cells. Each memory …
M Pasotti, R Zurla, A Cabrini, G Torelli - US Patent 9,893,689, 2018 - Google Patents
According to an embodiment, an operational amplifier includes a first amplifier stage coupled between an input node and an intermediate node, a second amplifier stage …