Excessive test power can cause multiple issues at manufacturing as well as during field test.
To reduce both shift and capture power during test, we propose a DFT-based approach …

Deterministic testing is by far the most interesting built-in self-test (BIST) technique because
of the minimal number of test patterns required and of the known fault coverage. However, it …

Excessive power during in-field testing can cause multiple issues, including invalidation of
the test results, over-heating, and damage to the circuit. In this paper, we evaluate the …

With the exponential increase of transistor counts, scan design encounters several problems
such as large test data volume, long test application time and high test power. In this paper …

摘要传统扫描链将所有扫描单元串联, 测试数据的移位路径较长, 导致测试移位功耗较大.
首次提出代表扫描结构, 它将传统扫描链或子链中的触发器改造成环形移位寄存器 …

This paper proposes a scan disabling-based BIST-aided scan test (BAST) scheme. In this
scheme, a pseudo-random pattern generator (PRPG) generates test vector for each slice in …

This paper proposes a novel power-aware scan architecture: DCScan. In this architecture,
the compatible scan cells are grouped into the same segment. Test data propagation in …

Scan tree techniques reduce test application time significantly by shifting test values into (out
from) the compatible flip-flops simultaneously. This paper proposes a novel scan tree …

Extended compatibilities scan tree technique reduces test application time and test power
drastically during shifting-in the same test data to the compatible scan cells by employing …

Though test application time and test power is reduced drastically in the extended
compatibility scan tree, the number of output is too large. This paper proposes a response …