The open-source and community-supported gem5 simulator is one of the most popular tools
for computer architecture research. This simulation infrastructure allows researchers to …

In this paper, we propos a new shared memory model: Transactionalmemory Coherence
and Consistency (TCC). TCC providesa model in which atomic transactions are always the …

Increases in on-chip communication delay and the large working sets of server and scientific
workloads complicate the design of the on-chip last-level cache for multicore processors …

Over the past ten years, as integrated circuits became increasingly more complex and
expensive, the industry began to embrace new design and reuse methodologies that are …

Many modern computer systems, including homogeneous and heterogeneous architectures,
support shared memory in hardware. In a shared memory system, each of the processor …

This paper presents CMP Cooperative Caching, a unified framework to manage a CMP's
aggregate on-chip cache resources. Cooperative caching combines the strengths of private …

Computer architects employ a series of performance optimizations at the micro-architecture
level. These optimizations are meant to be invisible to the programmer but they are implicitly …

For parallelism to become tractable for mass programmers, shared-memory languages and
environments must evolve to enforce disciplined practices that ban" wild shared-memory …

While scalable coherence has been extensively studied in the context of general purpose
chip multiprocessors (CMPs), GPU architectures present a new set of challenges …

Current state-of-the-art on-chip networks provide efficiency, high throughput, and low latency
for one-to-one (unicast) traffic. The presence of one-to-many (multicast) or one-to-all …