Enabling interposer-based disintegration of multi-core processors
Silicon interposers enable the integration of multiple stacks of in-package memory to provide
higher bandwidth or lower energy for memory accesses. Once the interposer has been paid …
higher bandwidth or lower energy for memory accesses. Once the interposer has been paid …
CACTI-3DD: Architecture-level modeling for 3D die-stacked DRAM main memory
Emerging 3D die-stacked DRAM technology is one of the most promising solutions for future
memory architectures to satisfy the ever-increasing demands on performance, power, and …
memory architectures to satisfy the ever-increasing demands on performance, power, and …
Demystifying complex workload-DRAM interactions: An experimental study
It has become increasingly difficult to understand the complex interactions between modern
applications and main memory, composed of Dynamic Random Access Memory (DRAM) …
applications and main memory, composed of Dynamic Random Access Memory (DRAM) …
3D-MAPS: 3D massively parallel processor with stacked memory
SK Lim, SK Lim - Design for High Performance, Low Power, and …, 2013 - Springer
This chapter describes the architecture, design, analysis, and simulation and measurement
results of the 3D-MAPS (3D massively parallel processor with stacked memory) chip built …
results of the 3D-MAPS (3D massively parallel processor with stacked memory) chip built …
Reducing memory access latency with asymmetric DRAM bank organizations
DRAM has been a de facto standard for main memory, and advances in process technology
have led to a rapid increase in its capacity and bandwidth. In contrast, its random access …
have led to a rapid increase in its capacity and bandwidth. In contrast, its random access …
Utility-based hybrid memory management
While the memory footprints of cloud and HPC applications continue to increase,
fundamental issues with DRAM scaling are likely to prevent traditional main memory …
fundamental issues with DRAM scaling are likely to prevent traditional main memory …
NoC architectures for silicon interposer systems: Why pay for more wires when you can get them (from your interposer) for free?
Silicon interposer technology (" 2.5 D" stacking) enables the integration of multiple memory
stacks with a processor chip, thereby greatly increasing in-package memory capacity while …
stacks with a processor chip, thereby greatly increasing in-package memory capacity while …
A 3D-stacked logic-in-memory accelerator for application-specific data intensive computing
This paper introduces a 3D-stacked logic-in-memory (LiM) system that integrates the 3D die-
stacked DRAM architecture with the application-specific LiM IC to accelerate important data …
stacked DRAM architecture with the application-specific LiM IC to accelerate important data …
Three dimensional circuit implementing machine trained network
SL Teig, K Duong - US Patent 11,176,450, 2021 - Google Patents
Some embodiments provide a three-dimensional (3D) cir cuit structure that has two or more
vertically stacked bonded layers with a machine-trained network on at least one bonded …
vertically stacked bonded layers with a machine-trained network on at least one bonded …
4.6 A 1/2.3 inch 20Mpixel 3-layer stacked CMOS Image Sensor with DRAM
T Haruta, T Nakajima, J Hashizume… - … Solid-State Circuits …, 2017 - ieeexplore.ieee.org
In recent years, the performance of cellphone cameras has improved, and is becoming
comparable to that of SLR cameras. However, the big difference between cellphone …
comparable to that of SLR cameras. However, the big difference between cellphone …