GenStore: A High-Performance and Energy-Efficient In-Storage Computing System for Genome Sequence Analysis
Read mapping is a fundamental, yet computationally-expensive step in many genomics
applications. It is used to identify potential matches and differences between fragments …
applications. It is used to identify potential matches and differences between fragments …
A monolithically-integrated chip-to-chip optical link in bulk CMOS
Silicon-photonics is an emerging technology that can overcome the tradeoffs faced by
traditional electrical I/O. Due to ballooning development costs for advanced CMOS nodes …
traditional electrical I/O. Due to ballooning development costs for advanced CMOS nodes …
Accelerating weather prediction using near-memory reconfigurable fabric
Ongoing climate change calls for fast and accurate weather and climate modeling. However,
when solving large-scale weather prediction simulations, state-of-the-art CPU and GPU …
when solving large-scale weather prediction simulations, state-of-the-art CPU and GPU …
A mostly-clean DRAM cache for effective hit speculation and self-balancing dispatch
Die-stacking technology allows conventional DRAM to be integrated with processors. While
numerous opportunities to make use of such stacked DRAM exist, one promising way is to …
numerous opportunities to make use of such stacked DRAM exist, one promising way is to …
A 1.2 V 8 Gb 8-channel 128 GB/s high-bandwidth memory (HBM) stacked DRAM with effective I/O test circuits
DU Lee, KW Kim, KW Kim, KS Lee… - IEEE Journal of Solid …, 2014 - ieeexplore.ieee.org
Motivated by a graphics memory system that achieves multiplied bandwidth by the number
of memories per system, HBM DRAM adopts a brand new architecture, with many technical …
of memories per system, HBM DRAM adopts a brand new architecture, with many technical …
Challenges and emerging solutions in testing TSV-based 2 1 over 2D-and 3D-stacked ICs
EJ Marinissen - 2012 Design, Automation & Test in Europe …, 2012 - ieeexplore.ieee.org
Through-Silicon Vias (TSVs) provide high-density, low-latency, and low-power vertical
interconnects through a thinned-down wafer substrate, thereby enabling the creation of 2.5 …
interconnects through a thinned-down wafer substrate, thereby enabling the creation of 2.5 …
Reliability of TSV interconnects: Electromigration, thermal cycling, and impact on above metal level dielectric
T Frank, S Moreau, C Chappaz, P Leduc… - Microelectronics …, 2013 - Elsevier
In this paper, reliability of Through Silicon via (TSV) interconnects is analyzed for two
technologies. First part presents an exhaustive analysis of Cu TSV-last approach of 2μm …
technologies. First part presents an exhaustive analysis of Cu TSV-last approach of 2μm …
Demystifying the characteristics of 3D-stacked memories: A case study for hybrid memory cube
Three-dimensional (3D)-stacking technology, which enables the integration of DRAM and
logic dies, offers high bandwidth and low energy consumption. This technology also …
logic dies, offers high bandwidth and low energy consumption. This technology also …
Large-scale 3D chips: Challenges and solutions for design automation, testing, and trustworthy integration
Three-dimensional (3D) integration of electronic chips has been advocated by both industry
and academia for many years. It is acknowledged as one of the most promising approaches …
and academia for many years. It is acknowledged as one of the most promising approaches …
Exploring DRAM organizations for energy-efficient and resilient exascale memories
The power target for exascale supercomputing is 20MW, with about 30% budgeted for the
memory subsystem. Commodity DRAMs will not satisfy this requirement. Additionally, the …
memory subsystem. Commodity DRAMs will not satisfy this requirement. Additionally, the …