CACTI-IO: CACTI with off-chip power-area-timing models
We describe CACTI-IO, an extension to CACTI [4] that includes power, area and timing
models for the IO and PHY of the off-chip memory interface for various server and mobile …
models for the IO and PHY of the off-chip memory interface for various server and mobile …
Design and analysis of 3D-MAPS (3D massively parallel processor with stacked memory)
This paper describes the architecture, design, analysis, and simulation and measurement
results of the 3D-MAPS (3D massively parallel processor with stacked memory) chip built …
results of the 3D-MAPS (3D massively parallel processor with stacked memory) chip built …
Supporting very large dram caches with compound-access scheduling and missmap
This work efficiently enables conventional block sizes for very large die-stacked DRAM
caches with two innovations: it makes hits faster with compound-access scheduling and …
caches with two innovations: it makes hits faster with compound-access scheduling and …
Interconnect-memory challenges for multi-chip, silicon interposer systems
Silicon interposer technology is promising for large-scale integration of memory within a
processor package. While past work on vertical, 3D-stacked memory allows a stack of …
processor package. While past work on vertical, 3D-stacked memory allows a stack of …
3D Compute circuit with high density z-axis interconnects
SL Teig, I Mohammed, K Duong, J Delacruz - US Patent 10,672,743, 2020 - Google Patents
Some embodiments of the invention provide a three-dimen sional (3D) circuit that is formed
by vertically stacking two or more integrated circuit (IC) dies to at least partially overlap. In …
by vertically stacking two or more integrated circuit (IC) dies to at least partially overlap. In …
Attaché: Towards ideal memory compression by mitigating metadata bandwidth overheads
Memory systems are becoming bandwidth constrained and data compression is seen as a
simple technique to increase their effective bandwidth. However, data compressionrequires …
simple technique to increase their effective bandwidth. However, data compressionrequires …
DRAMA: An architecture for accelerated processing near memory
A Farmahini-Farahani, JH Ahn… - IEEE Computer …, 2014 - ieeexplore.ieee.org
Improving energy efficiency is crucial for both mobile and high-performance computing
systems while a large fraction of total energy is consumed to transfer data between storage …
systems while a large fraction of total energy is consumed to transfer data between storage …
Near-memory computing on fpgas with 3d-stacked memories: Applications, architectures, and optimizations
The near-memory computing (NMC) paradigm has transpired as a promising method for
overcoming the memory wall challenges of future computing architectures. Modern systems …
overcoming the memory wall challenges of future computing architectures. Modern systems …
Thermal design and constraints for heterogeneous integrated chip stacks and isolation technology using air gap and thermal bridge
This paper summarizes the thermal challenges in conventional 3-D stacks and proposes a
novel stacking structure that eases the thermal problem. The objective of this paper is first to …
novel stacking structure that eases the thermal problem. The objective of this paper is first to …
A Homogeneous Scalable 3D Network-on-Chip Circuit With 326 MFlit/s 0.66 pJ/b Robust and Fault Tolerant Asynchronous 3D Links
P Vivet, Y Thonnart, R Lemaire… - IEEE Journal of Solid …, 2016 - ieeexplore.ieee.org
Future many cores, either for high performance computing or for embedded applications, are
facing the power wall, and cannot be scaled up using only the reduction of technology …
facing the power wall, and cannot be scaled up using only the reduction of technology …