Low temperature SoIC bonding and stacking technology for 12-/16-Hi high bandwidth memory (HBM)
MF Chen, CH Tsai, T Ku, WC Chiou… - IEEE Transactions on …, 2020 - ieeexplore.ieee.org
A low temperature system-on-integrated-chip (SoIC) bonding and stacking technology is
proposed and implemented for 3-D memory integration, such as 3-D static random access …
proposed and implemented for 3-D memory integration, such as 3-D static random access …
A monolithically-integrated optical receiver in standard 45-nm SOI
Integrated photonics has emerged as an I/O technology that can meet the throughput
demands of future many-core processors. Taking advantage of the low capacitance …
demands of future many-core processors. Taking advantage of the low capacitance …
3D compute circuit with high density Z-axis interconnects
SL Teig, I Mohammed, K Duong, J Delacruz - US Patent 10,672,744, 2020 - Google Patents
Some embodiments of the invention provide a three-dimen sional (3D) circuit that is formed
by vertically stacking two or more integrated circuit (IC) dies to at least partially overlap. In …
by vertically stacking two or more integrated circuit (IC) dies to at least partially overlap. In …
A survey of techniques for architecting DRAM caches
Recent trends of increasing core-count and memory/bandwidth-wall have led to major
overhauls in chip architecture. In face of increasing cache capacity demands, researchers …
overhauls in chip architecture. In face of increasing cache capacity demands, researchers …
Implementation of a binary neural network on a passive array of magnetic tunnel junctions
The increasing scale of neural networks and their growing application space have produced
demand for more energy-and memory-efficient artificial-intelligence-specific hardware …
demand for more energy-and memory-efficient artificial-intelligence-specific hardware …
3D processor
SL Teig, I Mohammed, K Duong, J Delacruz - US Patent 10,672,745, 2020 - Google Patents
Some embodiments of the invention provide a three-dimen sional (3D) circuit that is formed
by vertically stacking two or more integrated circuit (IC) dies to at least partially overlap. In …
by vertically stacking two or more integrated circuit (IC) dies to at least partially overlap. In …
TSV-based 3-D ICs: Design methods and tools
Vertically integrated circuits (3-D ICs) may revitalize Moore's law scaling which has slowed
down in recent years. 3-D stacking is an emerging technology that stacks multiple dies …
down in recent years. 3-D stacking is an emerging technology that stacks multiple dies …
Integrated 3D-stacked server designs for increasing physical density of key-value stores
A Gutierrez, M Cieslak, B Giridhar… - Proceedings of the 19th …, 2014 - dl.acm.org
Key-value stores, such as Memcached, have been used to scale web services since the
beginning of the Web 2.0 era. Data center real estate is expensive, and several industry …
beginning of the Web 2.0 era. Data center real estate is expensive, and several industry …
Training a probabilistic graphical model with resistive switching electronic synapses
Current large-scale implementations of deep learning and data mining require thousands of
processors, massive amounts of off-chip memory, and consume gigajoules of energy. New …
processors, massive amounts of off-chip memory, and consume gigajoules of energy. New …
An energy-efficient dram cache architecture for mobile platforms with pcm-based main memory
A long battery life is a first-class design objective for mobile devices, and main memory
accounts for a major portion of total energy consumption. Moreover, the energy consumption …
accounts for a major portion of total energy consumption. Moreover, the energy consumption …