Citadel: Efficiently protecting stacked memory from tsv and large granularity failures
PJ Nair, DA Roberts, MK Qureshi - ACM Transactions on Architecture …, 2016 - dl.acm.org
Stacked memory modules are likely to be tightly integrated with the processor. It is vital that
these memory modules operate reliably, as memory failure can require the replacement of …
these memory modules operate reliably, as memory failure can require the replacement of …
Omitting refresh: A case study for commodity and wide i/o drams
Dynamic Random Access Memories (DRAM) have a big impact on performance and
contribute significantly to the total power consumption in systems ranging from mobile …
contribute significantly to the total power consumption in systems ranging from mobile …
Resilient die-stacked DRAM caches
Die-stacked DRAM can provide large amounts of in-package, high-bandwidth cache
storage. For server and high-performance computing markets, however, such DRAM caches …
storage. For server and high-performance computing markets, however, such DRAM caches …
3D chip sharing power interconnect layer
J Delacruz, SL Teig, I Mohammed - US Patent 10,600,691, 2020 - Google Patents
Some embodiments of the invention provide a three-dimen sional (3D) circuit that is formed
by stacking two or more integrated circuit (IC) dies to at least partially overlap and to share …
by stacking two or more integrated circuit (IC) dies to at least partially overlap and to share …
Self repairing neural network
SL Teig, K Duong - US Patent 10,762,420, 2020 - Google Patents
Some embodiments of the invention provide an integrated circuit (IC) with a defect-tolerant
neural network. The neural network has one or more redundant neurons in some …
neural network. The neural network has one or more redundant neurons in some …
3D chip sharing power circuit
J Delacruz, SL Teig, I Mohammed… - US Patent 10,672,663, 2020 - Google Patents
Some embodiments of the invention provide a three-dimensional (3D) circuit that is formed
by stacking two or more integrated circuit (IC) dies to at least partially overlap and to share …
by stacking two or more integrated circuit (IC) dies to at least partially overlap and to share …
Post-bond testing of 2.5 D-SICs and 3D-SICs containing a passive silicon interposer base
CC Chi, EJ Marinissen, SK Goel… - 2011 IEEE International …, 2011 - ieeexplore.ieee.org
Through-Silicon Vias (TSVs) enable high-density, low-latency, and low-power interconnects
for system chips that consist of multiple dies. In “2.5 D” Stacked ICs (2.5 D-SICs), multiple …
for system chips that consist of multiple dies. In “2.5 D” Stacked ICs (2.5 D-SICs), multiple …
3D chip sharing data bus circuit
J Delacruz, SL Teig, I Mohammed - US Patent 10,600,780, 2020 - Google Patents
Some embodiments of the invention provide a three-dimen sional (3D) circuit that is formed
by stacking two or more integrated circuit (IC) dies to at least partially overlap and to share …
by stacking two or more integrated circuit (IC) dies to at least partially overlap and to share …
3D chip sharing clock interconnect layer
J Delacruz, SL Teig, I Mohammed… - US Patent 10,586,786, 2020 - Google Patents
Some embodiments of the invention provide a three-dimen sional (3D) circuit that is formed
by stacking two or more integrated circuit (IC) dies to at least partially overlap and to share …
by stacking two or more integrated circuit (IC) dies to at least partially overlap and to share …
Review of bumpless build cube (BBCube) using wafer-on-wafer (WOW) and chip-on-wafer (COW) for tera-scale three-dimensional integration (3DI)
T Ohba, K Sakui, S Sugatani, H Ryoson, N Chujo - Electronics, 2022 - mdpi.com
Bumpless Build Cube (BBCube) using Wafer-on-Wafer (WOW) and Chip-on-Wafer (COW)
for Tera-Scale Three-Dimensional Integration (3DI) is discussed. Bumpless interconnects …
for Tera-Scale Three-Dimensional Integration (3DI) is discussed. Bumpless interconnects …