The continuing scaling of transistors has increased the number of cores available in current
processors, and the number of cores is expected to continue to increase. In such many core …

Many of the pins on a modern chip are used for power delivery. If fewer pins were used to
supply the same current, the wires and pins used for power delivery would have to carry …

Wide I/O, the recent JEDEC DRAM standard, has created an opportunity for architects to
overcome the" memory wall" challenge. 2.5 D/3D integration enables Wide-IO to deliver high …

Some embodiments provide a three-dimensional (3D) cir cuit structure that has two or more
vertically stacked bonded layers with a machine-trained network on at least one bonded …

3D Integrated Circuit (3D-IC) opens architecture opportunities for improved SoC-to-memory
interconnect bandwidth between dies. This paper presents the design of a two-tier 3D-IC …

In upcoming architectures that stack processor and DRAM dies, temperatures are higher
because of the increased transistor density and the high inter-layer thermal resistance …

Practical silicon stacking requires pre-tested dies, but contact probing of TSV interconnects
requires much higher density, lower probing forces, and lower cost per pin than …

Some embodiments of the invention provide a three-dimensional (3D) circuit that is formed
by stacking two or more integrated circuit (IC) dies to at least partially overlap and to share …

Some embodiments of the invention provide a three-dimen sional (3D) circuit that is formed
by stacking two or more integrated circuit (IC) dies to at least partially overlap and to share …

Copper electro-chemical deposition (ECD) of through silicon via (TSV) is a key challenge of
3D integration. This paper presents a numerical modeling of TSV filling concerning the …