Electromigration behavior of 3D-IC TSV interconnects
T Frank, S Moreau, C Chappaz… - 2012 IEEE 62nd …, 2012 - ieeexplore.ieee.org
The electromigration (EM) behavior of Through Silicon Via (TSV) interconnects used for 3D
integration is studied. Impact of the TSV section size on EM lifetime and consideration of …
integration is studied. Impact of the TSV section size on EM lifetime and consideration of …
Time borrowing between layers of a three dimensional chip stack
SL Teig, K Duong, J Delacruz - US Patent 10,607,136, 2020 - Google Patents
Some embodiments of the invention provide a three-dimen sional (3D) circuit structure that
uses latches to transfer signals between two bonded circuit layers. In some embodi ments …
uses latches to transfer signals between two bonded circuit layers. In some embodi ments …
Face-to-face mounted IC dies with orthogonal top interconnect layers
EM Nequist, SL Teig, J Delacruz, I Mohammed… - US Patent …, 2020 - Google Patents
Some embodiments of the invention provide a three-dimen sional (3D) circuit that is formed
by stacking two or more integrated circuit (IC) dies to at least partially overlap and to share …
by stacking two or more integrated circuit (IC) dies to at least partially overlap and to share …
3D chip sharing data bus
J Delacruz, SL Teig, I Mohammed - US Patent 10,600,735, 2020 - Google Patents
Some embodiments of the invention provide a three-dimen sional (3D) circuit that is formed
by stacking two or more integrated circuit (IC) dies to at least partially overlap and to share …
by stacking two or more integrated circuit (IC) dies to at least partially overlap and to share …
3D chip with shared clock distribution network
J Delacruz, SL Teig, I Mohammed - US Patent 10,886,177, 2021 - Google Patents
Some embodiments of the invention provide a three-dimen sional (3D) circuit that is formed
by stacking two or more integrated circuit (IC) dies to at least partially overlap and to share …
by stacking two or more integrated circuit (IC) dies to at least partially overlap and to share …
Direct probing on large-array fine-pitch micro-bumps of a wide-I/O logic-memory interface
EJ Marinissen, B De Wachter, K Smith… - 2014 International …, 2014 - ieeexplore.ieee.org
In order to obtain acceptable compound stack yields for 2.5 D-and 3D-SICs, there is a need
to test the constituting dies before stacking. The non-bottom dies of these stacks have their …
to test the constituting dies before stacking. The non-bottom dies of these stacks have their …
Artificial intelligence processor with three-dimensional stacked memory
Described is a packaging technology to improve perfor mance of an Al processing system.
An IC package is provided which comprises: a substrate; a first die on the substrate, and a …
An IC package is provided which comprises: a substrate; a first die on the substrate, and a …
A 100GB/s wide I/O with 4096b TSVs through an active silicon interposer with in-place waveform capturing
S Takaya, M Nagata, A Sakai, T Kariya… - … Solid-State Circuits …, 2013 - ieeexplore.ieee.org
Three dimensional (3D) stacking of memory chips is a promising direction for implementing
memory systems in mobile applications and for low-cost high-performance computation. The …
memory systems in mobile applications and for low-cost high-performance computation. The …
Stacked IC structure with system level wiring on multiple sides of the IC die
I Mohammed, SL Teig, J Delacruz - US Patent 10,950,547, 2021 - Google Patents
US10950547B2 - Stacked IC structure with system level wiring on multiple sides of the IC die -
Google Patents US10950547B2 - Stacked IC structure with system level wiring on multiple …
Google Patents US10950547B2 - Stacked IC structure with system level wiring on multiple …
Optimizing GPU energy efficiency with 3D die-stacking graphics memory and reconfigurable memory interface
The performance of graphics processing unit (GPU) systems is improving rapidly to
accommodate the increasing demands of graphics and high-performance computing …
accommodate the increasing demands of graphics and high-performance computing …