DfT architecture and ATPG for Interconnect tests of JEDEC Wide-I/O memory-on-logic die stacks
S Deutsch, B Keller, V Chickermane… - 2012 IEEE …, 2012 - ieeexplore.ieee.org
Three-dimensional (3D) die stacking is an emerging integration technology which brings
benefits with respect to heterogeneous integration, inter-die interconnect density …
benefits with respect to heterogeneous integration, inter-die interconnect density …
Retention time measurements and modelling of bit error rates of WIDE I/O DRAM in MPSoCs
DRAM cells use capacitors as volatile and leaky bit storage elements. The time spent
without refreshing them is called retention time. It is well known that the retention time …
without refreshing them is called retention time. It is well known that the retention time …
Material innovation opportunities for 3D integrated circuits from a wireless application point of view
SQ Gu - MRS Bulletin, 2015 - cambridge.org
The mobile revolution has enabled broad applications with a faster response, small form
factors, and more data bandwidth, sensing, and processing power. The industry is pursuing …
factors, and more data bandwidth, sensing, and processing power. The industry is pursuing …
A 1.2 V 30nm 1.6 Gb/s/pin 4Gb LPDDR3 SDRAM with input skew calibration and enhanced control scheme
YC Bae, JY Park, SJ Rhee, SB Ko… - … Solid-State Circuits …, 2012 - ieeexplore.ieee.org
Mobile DRAM is widely adopted in battery-powered portable devices because of its low
power. Recently, in mobile devices such as smart phones and tablet PCs, higher …
power. Recently, in mobile devices such as smart phones and tablet PCs, higher …
More is less: Improving the energy efficiency of data movement via opportunistic use of sparse codes
Data movement over long and highly capacitive interconnects is responsible for a large
fraction of the energy consumed in nanometer ICs. DDRx, the most broadly adopted family …
fraction of the energy consumed in nanometer ICs. DDRx, the most broadly adopted family …
Full-chip signal integrity analysis and optimization of 3-D ICs
Through-silicon-via (TSV)-to-TSV coupling is a new phenomenon in 3-D ICs, and it becomes
a significant source of signal integrity problems. The existing studies on its extraction and …
a significant source of signal integrity problems. The existing studies on its extraction and …
Exploration and optimization of 3-D integrated DRAM subsystems
Energy efficiency is the major optimization criterion for systems-on-chip (SoCs) for mobile
devices (smartphones and tablets). Through silicon via (TSV) technology enables 3-D …
devices (smartphones and tablets). Through silicon via (TSV) technology enables 3-D …
A high-level DRAM timing, power and area exploration tool
In systems ranging from mobile devices to servers, DRAM has a big impact on performance
and contributes a significant part of the total consumed power. The performance and power …
and contributes a significant part of the total consumed power. The performance and power …
Full-chip multiple TSV-to-TSV coupling extraction and optimization in 3D ICs
TSV-to-TSV coupling is a new parasitic element in 3D ICs and can become a significant
source of signal integrity problem. Existing studies on its extraction, however, becomes …
source of signal integrity problem. Existing studies on its extraction, however, becomes …
Artificial intelligence processor with three-dimensional stacked memory
Described is a packaging technology to improve perfor mance of an Al processing system.
An IC package is provided which comprises: a substrate; a first die on the substrate, and a …
An IC package is provided which comprises: a substrate; a first die on the substrate, and a …