Efficient reliability management in SoCs-an approximate DRAM perspective
In today's computing systems Dynamic Random Access Memories (DRAMs) have a large
influence on performance and contribute significantly to the total power consumption. Thus …
influence on performance and contribute significantly to the total power consumption. Thus …
[PDF][PDF] Challenges in heterogeneous die-stacked and off-chip memory systems
GH Loh, N Jayasena, K Mcgrath… - 3rd Workshop on …, 2012 - researchgate.net
Die-stacking technology has the potential to provide significant relief from the Memory Wall
by providing a large amount of memory with a high-bandwidth, low-power interconnect. Past …
by providing a large amount of memory with a high-bandwidth, low-power interconnect. Past …
A 5.4-mW 4-Gb/s 5-band QPSK transceiver for frequency-division multiplexing memory interface
This paper presents a novel self-equalized and skewless frequency-division multiplexing
memory interface. To prove its feasibility, we have realized a 5-band QPSK transceiver in 40 …
memory interface. To prove its feasibility, we have realized a 5-band QPSK transceiver in 40 …
Near-DRAM acceleration with single-ISA heterogeneous processing in standard memory modules
H Asghari-Moghaddam, A Farmahini-Farahani… - IEEE Micro, 2016 - ieeexplore.ieee.org
Energy consumed for transferring data across the processor memory hierarchy constitutes a
large fraction of total system energy consumption, and this fraction has steadily increased …
large fraction of total system energy consumption, and this fraction has steadily increased …
Three-dimensional integration: A tutorial for designers
SS Iyer, T Kirihata - IEEE solid-state circuits magazine, 2015 - ieeexplore.ieee.org
There is a perception that classical semiconductor scaling is undergoing saturation and has
recently not been delivering on the historical expectations for cost, power, and performance …
recently not been delivering on the historical expectations for cost, power, and performance …
Energy optimization in 3D MPSoCs with wide-I/O DRAM using temperature variation aware bank-wise refresh
Heterogeneous 3D integrated systems with Wide-I/O DRAMs are a promising solution to
squeeze more functionality and storage bits into an ever decreasing volume. Unfortunately …
squeeze more functionality and storage bits into an ever decreasing volume. Unfortunately …
Heterogeneous 3D integration—Technology enabler toward future super-chip
M Koyanagi - 2013 IEEE International Electron Devices …, 2013 - ieeexplore.ieee.org
To overcome various concerns caused by scaling-down the device size, it is indispensable
to introduce a new concept of heterogeneous 3D integration called a super-chip in which …
to introduce a new concept of heterogeneous 3D integration called a super-chip in which …
Electrical circuit modeling and validation of through-silicon vias embedded in a silicon microfluidic pin-fin heat sink filled with deionized water
H Oh, M Swaminathan, GS May… - IEEE Transactions on …, 2020 - ieeexplore.ieee.org
This article presents the electrical circuit model of signal-ground through-silicon vias (TSVs)
in a silicon microfluidic pin-fin heat sink in which the pin-fins are surrounded by deionized …
in a silicon microfluidic pin-fin heat sink in which the pin-fins are surrounded by deionized …
Verifying the performance of the PCI local bus using symbolic techniques
Symbolic model checking is a successful technique for checking properties of large finite-
state systems. This method has been used to verify a number of real-world hardware …
state systems. This method has been used to verify a number of real-world hardware …
System and circuit level power modeling of energy-efficient 3D-stacked wide I/O DRAMs
JEDEC recently introduced its new standard for 3D-stacked Wide I/O DRAM memories,
which defines their architecture, design, features and timing behavior. With improved …
which defines their architecture, design, features and timing behavior. With improved …