Low‐power and high‐speed 13T SRAM cell using FinFETs

S Saxena, R Mehra - IET Circuits, Devices & Systems, 2017 - Wiley Online Library
Fin field‐effect transistors (FinFETs) are replacing the traditional planar metal–oxide–
semiconductor FETs (MOSFETs) because of superior capability in controlling short channel …

Area and power efficient 4-bit comparator design by using 1-bit full adder module

A Sharma, P Sharma - 2014 International Conference on …, 2014 - ieeexplore.ieee.org
In this paper an area and power efficient 56T 4-bit comparator design has been presented
by using GDI technique. The proposed 4-bit comparator design consist of 28 NMOS and 28 …

[PDF][PDF] Area efficient 1-bit comparator design by using hybridized full adder module based on PTL and GDI logic

A Sharma, R Singh, P Kajla - International Journal of Computer …, 2013 - academia.edu
In this paper an area efficient 17T 1-bit hybrid comparator design has been presented by
hybridizing PTL and GDI techniques. The proposed 1-bit comparator design consist of 9 …

[PDF][PDF] Performance analysis of magnitude comparator using different design techniques

M Aggarwal, R Mehra - International Journal of Computer …, 2015 - researchgate.net
Comparators are a basic design module and element in modern digital VLSI design, digital
signal processors and data processing application-specific integrated circuits. This paper …

[PDF][PDF] Energy Efficient CNTFET Based Full Adder Using Hybrid Logic

P Kaushal, R Mehra - … Journal on Recent and Innovation Trends …, 2017 - researchgate.net
Full Adder is the basic element for arithmetic operations used in Very Large Scale Integrated
(VLSI) circuits, therefore, optimization of 1-bit full adder cell improves the overall …

Ultra Low-Power Implementation of PTL based 1-Bit Full Adder Using CNTFET Technology

P Singh, U Sharma - … in Technology and Management for Social …, 2024 - ieeexplore.ieee.org
In this study, a 1-bit Full Adder (FA) is implemented by utilizing 2: 1 MUX based on Pass
Transistor Logic (PTL) structure using Carbon Nano Tube Field Effect Transistor (CNTFET) …

Implementation of Deep Learning Algorithms Through a Module Based Approach Using Multiplierless Architectures

S Eligar, V Eligar, N Iyer - 2022 3rd International Conference for …, 2022 - ieeexplore.ieee.org
Deep Learning algorithms are enabling the design of complex systems across multiple
domains. Conventional implementations of these algorithms relied on GPU based …

[PDF][PDF] Analysis and performance evaluation of 1-bit full adder using different topologies

V Wilson - International Journal of Engineering Research and …, 2017 - pnrsolution.org
An adder is a digital circuit that performs addition of numbers and it plays an important role
in today's digital world. In processors and other kinds of computing devices, Adders are used …

[PDF][PDF] Design analysis of full adder using cascade voltage switch logic

M Sharma, R Mehra - IOSR J VLSI Signal Process, 2016 - academia.edu
The paper presents a new design for full adder by utilizing the cascade voltage switch logic.
Adders are the basic building block for all the functional units of microprocessors and digital …

Analysis of Darlington pair amplifier at 90nm technology

R Singh, R Mehra - 2016 International Conference on …, 2016 - ieeexplore.ieee.org
The demand of transistors is rising in today's communication system having high data rate.
Transistors are used in many applications where high gain is needed by using very low …