Machine Learning and GPU Accelerated Sparse Linear Solvers for Transistor-Level Circuit Simulation: A Perspective Survey

Z Jin, W Li, Y Bai, T Wang, Y Lu… - 2024 29th Asia and …, 2024 - ieeexplore.ieee.org
Sparse linear solvers play a crucial role in transistor-level circuit simulation, especially for
large-scale post-layout circuit simulation when considering complex parasitic effects. As …

OSSP-PTA: An online stochastic stepping policy for PTA on reinforcement learning

D Niu, Y Dong, Z Jin, C Zhang, Q Li… - IEEE Transactions on …, 2023 - ieeexplore.ieee.org
The dc analysis is essential and still quite challenging in large-scale nonlinear circuit
simulation. Pseudo transient analysis (PTA) is a widely used and has great potential solver …

Toward energy-efficient sparse matrix-vector multiplication with near STT-MRAM computing architecture

Y Li, H Zhang, X Wang, H Cai, Y Zhang, S Lv… - Proceedings of the 28th …, 2023 - dl.acm.org
Sparse Matrix-Vector Multiplication (SpMV) is one of the vital computational primitives used
in modern workloads. SpMV performs memory access, leading to unnecessary data …

Worst-case power integrity prediction using convolutional neural network

X Dong, Y Chen, J Chen, Y Wang, J Li, T Ni… - ACM Transactions on …, 2023 - dl.acm.org
Power integrity analysis is an essential step in power distribution network (PDN) sign-off to
ensure the performance and reliability of chips. However, with the growing PDN size and …

Adaptive stepping pta for dc analysis based on reinforcement learning

Y Dong, D Niu, Z Jin, C Zhang, Q Li… - IEEE Transactions on …, 2022 - ieeexplore.ieee.org
Solving the DC operating point efficiently for large-scale nonlinear circuit is crucial and quite
challenging. Pseudo transient analysis (PTA) is a widely-used and promising DC solver in …

A fast method to estimate through-bump current for power delivery verification

C Zhuo, S Sun - IEEE Transactions on Computer-Aided Design …, 2022 - ieeexplore.ieee.org
Due to the mismatch between the package scaling and the relentless silicon technology
scaling, the limited power supply bumps have to bear more stresses on bump reliability. A …

Unleashing the Potential of Machine Learning: Harnessing the Dynamics of Supply Noise for Timing Sign-Off

Y Chen, X Dong, WK Shih… - 2023 IEEE/ACM …, 2023 - ieeexplore.ieee.org
With the continuously growing supply noise in advanced technologies, timing sign-off has
become increasingly challenging. On one hand, sign-off with the worst-case static supply …

Adaptive Transient Stepping Policy on Reinforcement Learning

L Xu, D Niu, Y Yang, A Wang, Z Jin… - … of Electronics Design …, 2023 - ieeexplore.ieee.org
Transient analysis (TA) is the foundation for nonlinear electronic circuit simulation, which
determines the time-domain response of the circuit over a specified time interval. However, it …

Agile Full-Chip Sign-Off in the Post-Moore Era

X Dong, S Sun, Z Chen, J Yang… - 2023 China …, 2023 - ieeexplore.ieee.org
Sign-off is a crucial step in the chip design flow to guarantee the performance and reliability
of chips prior to tape-out. However, the ever-growing integration density and voltage scaling …

[PDF][PDF] UnetPro: Combining Attention with Skip Connection in Unet for Efficient IR Drop Prediction

Z Qi, D Niu, W Wang, X Wu, C Yu, Z Jin - ssslab.cn
IR drop analysis plays a key role in chip design. Unlike conventional time-consuming
numerical analysis methods, which involve solving large-scale linear circuit equations …