A 28-GHz Series-Parallel Combined Doherty Power Amplifier with PBO Efficiency Enhancement in 40nm Bulk CMOS
J Gu, H Qin, G Jin, H Xu, W Liu, T Han… - 2022 IEEE MTT-S …, 2022 - ieeexplore.ieee.org
In this paper, a series-parallel combined Doherty power amplifier is proposed. The Doherty
architecture is adopted for PBO efficiency enhancement. The power-combining structure is …
architecture is adopted for PBO efficiency enhancement. The power-combining structure is …
A 57-64 GHz Two-Way Parallel-Combined Power Amplifier with 16.6 dBm Psat and 23.6% Peak PAE in 40nm Bulk CMOS
This paper presents an efficient and linear two-way parallel-combined CMOS power
amplifier (PA). A pair of over-neutralization cross-coupled capacitors are used to boost the …
amplifier (PA). A pair of over-neutralization cross-coupled capacitors are used to boost the …
A 26-39.5 GHz Two-Path Voltage-Combined Power Amplifier with Bandwidth Broadening Technique in 22nm FD-SOI
X Cao, T Wu, S Ma - … International Conference on Solid-State & …, 2022 - ieeexplore.ieee.org
This paper presents the analysis and design of a 26-39.5 GHz power amplifier. In order to
achieve high output power, we adopt the two-path voltage-combined topology. A voltage …
achieve high output power, we adopt the two-path voltage-combined topology. A voltage …
A Ka-band Power Amplifier Improving OP1dB through Gain Expansion Achieving 28.1% PAE
Y Chu, Z Liu, CH Li, Y Wu, H Liu, C Zhao… - … on Microwave and …, 2023 - ieeexplore.ieee.org
A two-stage Ka-band power amplifier (PA) is designed in 65-nm CMOS process, in which
the driver stage is biased in class-C region while the output stage is biased in class-AB …
the driver stage is biased in class-C region while the output stage is biased in class-AB …