This paper describes a fast-locking all-digital phase-locked loop (ADPLL) with dynamic loop
gain control and a phase self-alignment mechanism. Compared with conventional fast …

CMOS analog and mixed-signal phase-locked loops (PLL) are widely used in varies of the
system-on-chips (SoC) as the clock generator or frequency synthesizer. This paper presents …

In this paper, we propose a compact ring-oscillator-based self-biased phase-locked loop
(SBPLL) for system-on-chip (SoC) clock generation. It adopts the proposed triple-well NMOS …

In this paper, we propose a robust self-injecting injection-locked phase-locked loop (SI-
ILPLL). It adopts a phase alignment loop (PAL) based on a subsampling phase frequency …

Miniaturization in the geometry of CMOS technology improves IC performance but beyond
certain limit, scaling of CMOS may be quite challenging due to various short channel effects …