Future GPUs and other high-performance throughput processors will require multiple TB/s of
bandwidth to DRAM. Satisfying this bandwidth demand within an acceptable energy budget …

This paper proposes an energy-efficient, high-throughput DRAM architecture for GPUs and
throughput processors. In these systems, requests from thousands of concurrent threads …

This paper introduces a tagless cache architecture for large in-package DRAM caches. The
conventional die-stacked DRAM cache has both a TLB and a cache tag array, which are …

3D-stacked memory devices with processing logic can help alleviate the memory bandwidth
bottleneck in GPUs. However, in order for such Near-Data Processing (NDP) memory stacks …

Efficient cache tag management is a primary design objective for large, in-package DRAM
caches. Recently, Tagless DRAM Caches (TDCs) have been proposed to completely …

Recent advances in in-vehicle technologies have paved way to a new era of connectivity.
Vehicle manufacturers have already deployed various technologies for driving assistance …

Owing to increasing demand of faster and larger DRAM system, the DRAM system accounts
for a large portion of the total power consumption of computing systems. As memory traffic …

There are two major sources of inefficiency in computing systems that use modern DRAM
devices as main memory. First, due to coarse-grained data transfers (size of a cache block …

A promising recent development that can provide continued scaling of performance is the
ability to stack multiple DRAM layers on a multi-core processor die. This paper analyzes the …

Computer servers are equipped with an increasing number of memory modules each with
more capacity, making main-memory systems now the second most energy-consuming …