Continuing advances in semiconductor technology, coupled with an increasing concern for
energy efficiency, have led to an industry-wide shift in focus towards modular designs that …

Correctness is a first-order concern in the design of computer systems. For multiprocessors,
a primary correctness concern is the deadlock-free operation of the network and its …

Network on chip (NoC) is a scalable interconnection architecture for ever increasing
communication demand between processing cores. However, in nanoscale technology size …

Moore's Law scaling is continuing to yield even higher transistor density with each
succeeding process generation, leading to today's multi-core Chip Multi-Processors (CMPs) …

Network-on-chips (NoCs) are quickly becoming the standard communication fabric for multi-
core systems. As technology continues to scale down into the nanometer regime, device …

In emerging 3D NoC-based chip multiprocessors (CMPs), aging in circuits due to bias
temperature instability (BTI) stress is expected to cause gate-delay degradation that, if left …

Technology scaling leads to the reliability issue as a primary concern in Network-on-Chip
(NoC) design. We observe that due to routing algorithm some routers age much faster than …

Two sets of points in d-dimensional space are given: a data set D consisting of N points, and
a pattern set or probe P consisting of k points. We address the problem of determining …

The movement toward 3D fabrication coupled with Network-on-Chip (NoC) aims to improve
area, performance, power, and scalability of many-core systems. However, reliability issue …

As transistor scales down to sub-nanometer and processing cores with billions of transistors
are integrated, reliable and energy-efficient Network-on-Chip (NoC) architectures are critical …