Figaro: Improving system performance via fine-grained in-dram data relocation and caching
Main memory, composed of DRAM, is a performance bottleneck for many applications, due
to the high DRAM access latency. In-DRAM caches work to mitigate this latency by …
to the high DRAM access latency. In-DRAM caches work to mitigate this latency by …
QUAC-TRNG: High-throughput true random number generation using quadruple row activation in commodity DRAM chips
True random number generators (TRNG) sample random physical processes to create large
amounts of random numbers for various use cases, including security-critical cryptographic …
amounts of random numbers for various use cases, including security-critical cryptographic …
Improving 3D NAND flash memory lifetime by tolerating early retention loss and process variation
Compared to planar (ie, two-dimensional) NAND flash memory, 3D NAND flash memory
uses a new flash cell design, and vertically stacks dozens of silicon layers in a single chip …
uses a new flash cell design, and vertically stacks dozens of silicon layers in a single chip …
Benchmarking memory-centric computing systems: Analysis of real processing-in-memory hardware
Many modern workloads such as neural network inference and graph processing are
fundamentally memory-bound. For such workloads, data movement between memory and …
fundamentally memory-bound. For such workloads, data movement between memory and …
Energy efficient computing systems: Architectures, abstractions and modeling to techniques and standards
Computing systems have undergone a tremendous change in the last few decades with
several inflexion points. While Moore's law guided the semiconductor industry to cram more …
several inflexion points. While Moore's law guided the semiconductor industry to cram more …
Analysis of dawnbench, a time-to-accuracy machine learning performance benchmark
Researchers have proposed hardware, software, and algorithmic optimizations to improve
the computational performance of deep learning. While some of these optimizations perform …
the computational performance of deep learning. While some of these optimizations perform …
Hammerscope: Observing dram power consumption using rowhammer
The constant reduction in memory cell sizes has increased memory density and reduced
power consumption, but has also affected its reliability. The Rowhammer attack exploits this …
power consumption, but has also affected its reliability. The Rowhammer attack exploits this …
HiRA: Hidden row activation for reducing refresh latency of off-the-shelf DRAM chips
DRAM is the building block of modern main memory systems. DRAM cells must be
periodically refreshed to prevent data loss. Refresh operations degrade system performance …
periodically refreshed to prevent data loss. Refresh operations degrade system performance …
What your DRAM power models are not telling you: Lessons from a detailed experimental study
Main memory (DRAM) consumes as much as half of the total system power in a computer
today, due to the increasing demand for memory capacity and bandwidth. There is a …
today, due to the increasing demand for memory capacity and bandwidth. There is a …
The reach profiler (reaper) enabling the mitigation of dram retention failures via profiling at aggressive conditions
Modern DRAM-based systems suffer from significant energy and latency penalties due to
conservative DRAM refresh standards. Volatile DRAM cells can retain information across a …
conservative DRAM refresh standards. Volatile DRAM cells can retain information across a …