D-RaNGe: Using commodity DRAM devices to generate true random numbers with low latency and high throughput

JS Kim, M Patel, H Hassan, L Orosa… - 2019 IEEE International …, 2019 - ieeexplore.ieee.org
We propose a new DRAM-based true random number generator (TRNG) that leverages
DRAM cells as an entropy source. The key idea is to intentionally violate the DRAM access …

Design-induced latency variation in modern DRAM chips: Characterization, analysis, and latency reduction mechanisms

D Lee, S Khan, L Subramanian, S Ghose… - Proceedings of the …, 2017 - dl.acm.org
Variation has been shown to exist across the cells within a modern DRAM chip. Prior work
has studied and exploited several forms of variation, such as manufacturing-process-or …

PiDRAM: A Holistic End-to-end FPGA-based Framework for Processing-in-DRAM

A Olgun, JG Luna, K Kanellopoulos, B Salami… - ACM Transactions on …, 2022 - dl.acm.org
Commodity DRAM-based processing-using-memory (PuM) techniques that are supported
by off-the-shelf DRAM chips present an opportunity for alleviating the data movement …

DRAM bender: An extensible and versatile FPGA-based infrastructure to easily test state-of-the-art DRAM chips

A Olgun, H Hassan, AG Yağlıkçı… - … on Computer-Aided …, 2023 - ieeexplore.ieee.org
To understand and improve DRAM performance, reliability, security, and energy efficiency,
prior works study characteristics of commodity DRAM chips. Unfortunately, state-of-the-art …

Demystifying complex workload-DRAM interactions: An experimental study

S Ghose, T Li, N Hajinazar, DS Cali… - Proceedings of the ACM on …, 2019 - dl.acm.org
It has become increasingly difficult to understand the complex interactions between modern
applications and main memory, composed of Dynamic Random Access Memory (DRAM) …

In-DRAM bulk bitwise execution engine

V Seshadri, O Mutlu - arXiv preprint arXiv:1905.09822, 2019 - arxiv.org
Many applications heavily use bitwise operations on large bitvectors as part of their
computation. In existing systems, performing such bulk bitwise operations requires the …

Bit-exact ECC recovery (BEER): Determining DRAM on-die ECC functions by exploiting DRAM data retention characteristics

M Patel, JS Kim, T Shahroodi… - 2020 53rd Annual …, 2020 - ieeexplore.ieee.org
Increasing single-cell DRAM error rates have pushed DRAM manufacturers to adopt on-die
error-correction coding (ECC), which operates entirely within a DRAM chip to improve …

Detecting and mitigating data-dependent DRAM failures by exploiting current memory content

S Khan, C Wilkerson, Z Wang, AR Alameldeen… - Proceedings of the 50th …, 2017 - dl.acm.org
DRAM cells in close proximity can fail depending on the data content in neighboring cells.
These failures are called data-dependent failures. Detecting and mitigating these failures …

Crow: A low-cost substrate for improving dram performance, energy efficiency, and reliability

H Hassan, M Patel, JS Kim, AG Yaglikci… - Proceedings of the 46th …, 2019 - dl.acm.org
DRAM has been the dominant technology for architecting main memory for decades. Recent
trends in multi-core system design and large-dataset applications have amplified the role of …

Utility-based hybrid memory management

Y Li, S Ghose, J Choi, J Sun, H Wang… - … Conference on Cluster …, 2017 - ieeexplore.ieee.org
While the memory footprints of cloud and HPC applications continue to increase,
fundamental issues with DRAM scaling are likely to prevent traditional main memory …