Concurrent data structures for near-memory computing

Z Liu, I Calciu, M Herlihy, O Mutlu - … of the 29th ACM Symposium on …, 2017 - dl.acm.org
The performance gap between memory and CPU has grown exponentially. To bridge this
gap, hardware architects have proposed near-memory computing (also called processing-in …

On the resilience of rtl nn accelerators: Fault characterization and mitigation

B Salami, OS Unsal… - 2018 30th International …, 2018 - ieeexplore.ieee.org
Machine Learning (ML) is making a strong resurgence in tune with the massive generation
of unstructured data which in turn requires massive computational resources. Due to the …

Solar-DRAM: Reducing DRAM access latency by exploiting the variation in local bitlines

J Kim, M Patel, H Hassan… - 2018 IEEE 36th …, 2018 - ieeexplore.ieee.org
DRAM latency is a major bottleneck for many applications in modern computing systems. In
this work, we rigorously characterize the effects of reducing DRAM access latency on 282 …

Functionally-Complete Boolean Logic in Real DRAM Chips: Experimental Characterization and Analysis

İE Yüksel, YC Tuğrul, A Olgun… - … Symposium on High …, 2024 - ieeexplore.ieee.org
Processing-using-DRAM (PuD) is an emerging paradigm that leverages the analog
operational properties of DRAM circuitry to enable massively parallel in-DRAM computation …

Enabling the adoption of processing-in-memory: Challenges, mechanisms, future research directions

S Ghose, K Hsieh, A Boroumand… - arXiv preprint arXiv …, 2018 - arxiv.org
Poor DRAM technology scaling over the course of many years has caused DRAM-based
main memory to increasingly become a larger system bottleneck. A major reason for the …

Respawn: Energy-efficient fault-tolerance for spiking neural networks considering unreliable memories

RVW Putra, MA Hanif… - 2021 IEEE/ACM …, 2021 - ieeexplore.ieee.org
Spiking neural networks (SNNs) have shown a potential for having low energy with
unsupervised learning capabilities due to their biologically-inspired computation. However …

CLR-DRAM: A low-cost DRAM architecture enabling dynamic capacity-latency trade-off

H Luo, T Shahroodi, H Hassan, M Patel… - 2020 ACM/IEEE 47th …, 2020 - ieeexplore.ieee.org
DRAM is the prevalent main memory technology, but its long access latency can limit the
performance of many workloads. Although prior works provide DRAM designs that reduce …

An experimental study of reduced-voltage operation in modern FPGAs for neural network acceleration

B Salami, EB Onural, IE Yuksel, F Koc… - 2020 50th Annual …, 2020 - ieeexplore.ieee.org
We empirically evaluate an undervolting technique, ie, underscaling the circuit supply
voltage below the nominal level, to improve the power-efficiency of Convolutional Neural …

SpyHammer: Using RowHammer to remotely spy on temperature

L Orosa, U Rührmair, AG Yaglikci, H Luo… - arXiv preprint arXiv …, 2022 - arxiv.org
RowHammer is a DRAM vulnerability that can cause bit errors in a victim DRAM row by just
accessing its neighboring DRAM rows at a high-enough rate. Recent studies demonstrate …

Codic: A low-cost substrate for enabling custom in-dram functionalities and optimizations

L Orosa, Y Wang, M Sadrosadati, JS Kim… - 2021 ACM/IEEE 48th …, 2021 - ieeexplore.ieee.org
DRAM is the dominant main memory technology used in modern computing systems.
Computing systems implement a memory controller that interfaces with DRAM via DRAM …