There are three domains in a modern thermally-constrained mobile system-on-chip (SoC):
compute, IO, and memory. We observe that a modern SoC typically allocates a fixed power …

Long DRAM access latency is a major bottleneck for system performance. In order to access
data in DRAM, a memory controller (1) activates (ie, opens) a row of DRAM cells in a cell …

Deep neural network (DNN) accelerators received considerable attention in past years due
to saved energy compared to mainstream hardware. Low-voltage operation of DNN …

DRAM vendors utilize On-Die Error Correction Codes (OD-ECC) to correct random bit errors
internally. Meanwhile, system companies utilize Rank-Level ECC (RL-ECC) to protect data …

Spiking Neural Networks (SNNs) have the potential for achieving low energy consumption
due to their biologically sparse computation. Several studies have shown that the off-chip …

NAND flash memory is ubiquitous in everyday life today because its capacity has
continuously increased and cost has continuously decreased over decades. This positive …

With frequent software-induced activations on DRAM rows, bit flips can occur on their
physically adjacent rows (ie, RowHammer). Existing studies leverage FPGA platforms to …

In the Advent of the Internet of Things (IoT), embedded architecture takes an important
dimension in terms of energy and accomplishment. The embedded system needs more and …

ABSTRACT A DRAM chip requires periodic refresh operations to prevent data loss due to
charge leakage in DRAM cells. Refresh operations incur significant performance overhead …

The memory controller is in charge of managing DRAM maintenance operations (eg,
refresh, RowHammer protection, memory scrubbing) in current DRAM chips. Implementing …