EnforceSNN: Enabling resilient and energy-efficient spiking neural network inference considering approximate DRAMs for embedded systems
Spiking Neural Networks (SNNs) have shown capabilities of achieving high accuracy under
unsupervised settings and low operational power/energy due to their bio-plausible …
unsupervised settings and low operational power/energy due to their bio-plausible …
Aging-aware request scheduling for non-volatile main memory
Modern computing systems are embracing non-volatile memory (NVM) to implement high-
capacity and low-cost main memory. Elevated operating voltages of NVM accelerate the …
capacity and low-cost main memory. Elevated operating voltages of NVM accelerate the …
Intelligent architectures for intelligent computing systems
O Mutlu - 2021 Design, Automation & Test in Europe …, 2021 - ieeexplore.ieee.org
Computing is bottlenecked by data. Large amounts of application data overwhelm storage
capability, communication capability, and computation capability of the modern machines …
capability, communication capability, and computation capability of the modern machines …
Reliability issues in flash-memory-based solid-state drives: Experimental analysis, mitigation, recovery
NAND flash memory is ubiquitous in everyday life today because its capacity has
continuously increased and cost has continuously decreased over decades. This positive …
continuously increased and cost has continuously decreased over decades. This positive …
Understanding power consumption and reliability of high-bandwidth memory with voltage underscaling
Modern computing devices employ High-Bandwidth Memory (HBM) to meet their memory
bandwidth requirements. An HBM-enabled device consists of multiple DRAM layers stacked …
bandwidth requirements. An HBM-enabled device consists of multiple DRAM layers stacked …
Revisiting row hammer: A deep dive into understanding and resolving the issue
H Wang, X Peng, Z Liu, X Huang, T Li, B Yang… - Microelectronics …, 2024 - Elsevier
Row hammer is a vulnerability in Dynamic Random Access Memory (DRAM) chips, whereby
repeatedly accessing a specific row in the DRAM chip may cause bit flips in memory cells …
repeatedly accessing a specific row in the DRAM chip may cause bit flips in memory cells …
Workload-aware dram error prediction using machine learning
L Mukhanov, K Tovletoglou… - 2019 IEEE …, 2019 - ieeexplore.ieee.org
The aggressive scaling of technology may have helped to meet the growing demand for
higher memory capacity and density, but has also made DRAM cells more prone to errors …
higher memory capacity and density, but has also made DRAM cells more prone to errors …
Can ternary computing improve information assurance?
B Cambou, PG Flikkema, J Palmer, D Telesca… - Cryptography, 2018 - mdpi.com
Modern computer microarchitectures build on well-established foundations that have
encouraged a pattern of computational homogeneity that many cyberattacks depend on. We …
encouraged a pattern of computational homogeneity that many cyberattacks depend on. We …
PreLatPUF: Exploiting DRAM latency variations for generating robust device signatures
Physically unclonable functions (PUFs) are potential security blocks to generate unique and
more secure keys in low-cost cryptographic applications. Dynamic random-access memory …
more secure keys in low-cost cryptographic applications. Dynamic random-access memory …
Random and adversarial bit error robustness: Energy-efficient and secure DNN accelerators
Deep neural network (DNN) accelerators received considerable attention in recent years
due to the potential to save energy compared to mainstream hardware. Low-voltage …
due to the potential to save energy compared to mainstream hardware. Low-voltage …