The processing-in-memory paradigm: Mechanisms to enable adoption
Performance improvements from DRAM technology scaling have been lagging behind the
improvements from logic technology scaling for many years. As application demand for main …
improvements from logic technology scaling for many years. As application demand for main …
ITAP: Idle-time-aware power management for GPU execution units
Graphics Processing Units (GPUs) are widely used as the accelerator of choice for
applications with massively data-parallel tasks. However, recent studies show that GPUs …
applications with massively data-parallel tasks. However, recent studies show that GPUs …
Techniques for reducing the connected-standby energy consumption of mobile devices
Modern mobile devices, such as smartphones, tablets, and laptops, are idle most of the time
but they remain connected to communication channels even when idle. This operation mode …
but they remain connected to communication channels even when idle. This operation mode …
Memory-based combination PUFs for device authentication in embedded systems
Embedded systems play a crucial role in fueling the growth of the Internet-of-Things (IoT) in
application domains such as health care, home automation, transportation, etc. However …
application domains such as health care, home automation, transportation, etc. However …
CPU-GPU-memory DVFS for power-efficient MPSoC in mobile cyber physical systems
Most modern mobile cyber-physical systems such as smartphones come equipped with
multi-processor systems-on-chip (MPSoCs) with variant computing capacity both to cater to …
multi-processor systems-on-chip (MPSoCs) with variant computing capacity both to cater to …
HaRMony: Heterogeneous-reliability memory and QoS-aware energy management on virtualized servers
K Tovletoglou, L Mukhanov, DS Nikolopoulos… - Proceedings of the …, 2020 - dl.acm.org
The explosive growth of data increases the storage needs, especially within servers, making
DRAM responsible for more than 40% of the total system power. Such a reality has made …
DRAM responsible for more than 40% of the total system power. Such a reality has made …
Dstress: Automatic synthesis of dram reliability stress viruses using genetic algorithms
L Mukhanov, DS Nikolopoulos… - 2020 53rd Annual …, 2020 - ieeexplore.ieee.org
Failures become inevitable in DRAM devices, which is a major obstacle for scaling down the
density of cells in future DRAM technologies. These failures can be detected by specific …
density of cells in future DRAM technologies. These failures can be detected by specific …
OSM: Off-chip shared memory for GPUs
S Darabi, E Yousefzadeh-Asl-Miandoab… - … on Parallel and …, 2022 - ieeexplore.ieee.org
Graphics Processing Units (GPUs) employ a shared memory, a software-managed cache for
programmers, in each streaming multiprocessor to accelerate data sharing among the …
programmers, in each streaming multiprocessor to accelerate data sharing among the …
On the resilience of deep learning for reduced-voltage FPGAs
Deep Neural Networks (DNNs) are inherently computation-intensive and also power-
hungry. Hardware accelerators such as Field Programmable Gate Arrays (FPGAs) are a …
hungry. Hardware accelerators such as Field Programmable Gate Arrays (FPGAs) are a …
Enabling Effective Error Mitigation in Memory Chips That Use On-Die Error-Correcting Codes
M Patel - arXiv preprint arXiv:2204.10387, 2022 - arxiv.org
Improvements in main memory storage density are primarily driven by process technology
scaling, which negatively impacts reliability by exacerbating various circuit-level error …
scaling, which negatively impacts reliability by exacerbating various circuit-level error …