Este trabalho consiste no projeto e implementação em CMOS de um circuito integrado digital para geração de sinais, denominado Oscilador Controlado Numericamente. O …
B Esposito, HS Neoh - US Patent 7,598,790, 2009 - Google Patents
(22) Filed: Jan. 30, 2008(57)(51) Int. Cl. A clock synthesis circuit includes a polyphase numerically G {} 6F I/04(2006.01) controlled oscillator, an extraction circuit, and a clock …
A very simple and efficient scheme for jitter reduction is proposed for a carrier frequency recovery loop using phase differential frequency estimation, which estimates the current …
J Bayard - Review of scientific instruments, 2007 - pubs.aip.org
We propose a new method to build a biphase sinusoidal generator which provides two signals: v 1= V m sin (ω t) and v 2= V m sin (ω t+ φ), where V m, ω, and φ are digitally …
No intervalo de valores de frequência de poucos kHz até 1 MHz, nomeado às vezes como região de dispersão?, as estruturas das células são o principal determinante da impedância …
A Iftikhar - Edited by: Prof. RE Sheriff - academia.edu
This paper describes general overview of the DDC by explaining its individual blocks (NCO, CFIR, PFIR, and CIC) and their implementation in MATLAB SIMULINK and XILINX system …
J Bayard - Review of Scientific Instruments, 2010 - pubs.aip.org
This paper describes a biphase sinusoidal generator which provides two signals: v ref= VM sin (ω t) and v out= VM sin (ω t+ Δ Φ), where Δ Φ is in the range 0, π/2 or− π/2, 0 and is …
Dans le cadre de ce travail, nous avons analysé les performances d'un récepteur GPS numérique reprogrammable. Avec le développement de plus en plus rapide des systèmes …
H Lim - COIN-NGNCON 2006-The Joint International …, 2006 - ieeexplore.ieee.org
Both the steady-state and transient performances of a carrier frequency recovery loop are improved by simply overlapping the observation intervals for successive frequency offset …