Enriching object detection with 2d-3d registration and continuous viewpoint estimation
C Bongsoo Choy, M Stark… - Proceedings of the …, 2015 - openaccess.thecvf.com
A large body of recent work on object detection has focused on exploiting 3D CAD model
databases to improve detection performance. Many of these approaches work by aligning …
databases to improve detection performance. Many of these approaches work by aligning …
Formal verification of pipelined microprocessors
D Kroening - 2001 - publikationen.sulb.uni-saarland.de
Subject of this thesis is the formal verification of pipelined microprocessors. This includes
processors with state of the art schedulers, such as the Tomasulo scheduler and …
processors with state of the art schedulers, such as the Tomasulo scheduler and …
Model checking the flexray physical layer protocol
The FlexRay standard, developed by a cooperation of leading companies in the automotive
industry, is a robust communication protocol for distributed components in modern vehicles …
industry, is a robust communication protocol for distributed components in modern vehicles …
[图书][B] System Architecture
W Paul, C Baumann, P Lutsyk, S Schmaltz - 2016 - Springer
This text contains the lecture notes of a class we teach in Saarbrücken to first-year students
within a single semester. The purpose of the class is simple: to exhibit constructions of• a …
within a single semester. The purpose of the class is simple: to exhibit constructions of• a …
Towards the formal verification of lower system layers in automotive systems
S Beyer, P Bohm, M Gerke, M Hillebrand… - … on Computer Design, 2005 - ieeexplore.ieee.org
The mission of the Verisoft project is (i) to develop techniques, which permit the pervasive
formal verification of computer systems comprising hardware, system software …
formal verification of computer systems comprising hardware, system software …
[图书][B] A Pipelined Multi-core MIPS Machine: Hardware Implementation and Correctness Proof
M Kovalev, SM Müller, WJ Paul - 2014 - books.google.com
This monograph is based on the third author's lectures on computer architecture, given in
the summer semester 2013 at Saarland University, Germany. It contains a gate level …
the summer semester 2013 at Saarland University, Germany. It contains a gate level …
[PDF][PDF] On the complexity of booth recoding
WJ Paul, PM Seidel - Proc. 3rd Conf. On Real Numbers and Computers, 1998 - Citeseer
On The Complexity Of Booth Recoding Abstract 1 Introduction Page 1 On The Complexity
Of Booth Recoding Wolfgang J. Paul Peter-Michael Seidel y Abstract We formalize and …
Of Booth Recoding Wolfgang J. Paul Peter-Michael Seidel y Abstract We formalize and …
[图书][B] Logik und Algebra: eine praxisbezogene Einführung für Informatiker und Wirtschaftsinformatiker
F Staab - 2012 - books.google.com
Page 1 Page 2 Page 3 Logik und Algebra Eine praxisbezogene Einführung für Informatiker und
Wirtschaftsinformatiker von Prof. Dr. Frank Staab Duale Hochschule Baden-Württemberg …
Wirtschaftsinformatiker von Prof. Dr. Frank Staab Duale Hochschule Baden-Württemberg …
To Booth or not to Booth
WJ Paul, PM Seidel - Integration, 2002 - Elsevier
Booth Recoding is a commonly used technique to recode one of the operands in binary
multiplication. In this way the implementation of a multipliers' adder tree can be improved in …
multiplication. In this way the implementation of a multipliers' adder tree can be improved in …
[PDF][PDF] Formal verification of an IEEE floating point adder
C Berg - Master's Thesis, Saarland University, Germany, 2001 - df7cb.de
Abstract Our group at Saarland University is formally verifying the correctness of a complete
microprocessor called VAMP. The PVS theorem prover is used to specify the circuit …
microprocessor called VAMP. The PVS theorem prover is used to specify the circuit …