Semiconductor on insulator structure comprising a plasma nitride layer and method of manufacture thereof

SJ Kweskin - US Patent 11,114,332, 2021 - Google Patents
US11114332B2 - Semiconductor on insulator structure comprising a plasma nitride layer and
method of manufacture thereof - Google Patents US11114332B2 - Semiconductor on insulator …

Co-packaging photonic integrated circuits and application specific integrated circuits

C Doerr, E Swanson, D Vermeulen, S Azemati… - US Patent …, 2018 - Google Patents
Disclosed herein are designs, structures and techniques for advanced packaging of multi-
function photonic integrated circuits that allow such high-performance multi-function …

Semiconductor memory device and method of fabricating the same

J Kim, D Kim, D Lee - US Patent 10,903,216, 2021 - Google Patents
Disclosed are a semiconductor memory device and a method of fabricating the same. The
device may include a first substrate comprising a cell array region, a first interlayer insulating …

Method for fabrication of a semiconductor device and structure

Z Or-Bach, DC Sekar, B Cronquist, I Beinglass… - US Patent …, 2012 - Google Patents
2020-10-20 Assigned to MONOLITHIC 3D INC. reassignment MONOLITHIC 3D INC.
ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors …

Optoelectronic ball grid array package with fiber

C Doerr - US Patent 11,360,278, 2022 - Google Patents
A photonic integrated circuit may be coupled to an optical fiber and packaged. The optical
fiber may be supported by a fiber holder during a solder reflow process performed to mount …

Die stack with optical TSVs

PH Pelley, TA Stephens, MB McShane - US Patent 9,094,135, 2015 - Google Patents
6,477,303 6,556,285 6,650,810 6,686,993 6,690,845 6,753,037 6,765,396 6,813,584
6,850,081 6,897,663 6,909,830 6,936,491 6,950,570 6,999,651 7,016,564 7,020,363 …

Method of manufacturing high resistivity semiconductor-on-insulator wafers with charge trapping layers

I Peidous, JL Libbert, S Kommu, AM Jones… - US Patent …, 2019 - Google Patents
A method of preparing a single crystal semiconductor handle wafer in the manufacture of a
semiconductor-on-insulator device is provided. The single crystal semiconductor handle …

Logic circuit block layouts with dual-side processing

S Goktepeli, J Richaud - US Patent 10,083,963, 2018 - Google Patents
HOIL 21/8238(2006. 01) HOIL 29/06(2006. 01) HOIL 29/423(2006. 01) HOIL 21/768(2006.
01) HOIL 21/822(2006. 01) HOIL 27/06(2006. 01) US CI. CPC.... HOIL 27/0924 (2013. 01); …

Process flow for manufacturing semiconductor on insulator structures in parallel

I Peidous, AM Jones, S Kommu, JL Libbert - US Patent 9,831,115, 2017 - Google Patents
US9831115B2 - Process flow for manufacturing semiconductor on insulator structures in
parallel - Google Patents US9831115B2 - Process flow for manufacturing semiconductor on …

High resistivity SOI wafers and a method of manufacturing thereof

I Peidous, S Kommu, G Wang, SG Thomas - US Patent 10,079,170, 2018 - Google Patents
A high resistivity single crystal semiconductor handle structure for use in the manufacture of
SOI structure is provided. The handle structure comprises an intermediate semiconductor …