With the increasing concern of the security on high performance multiprocessor enterprise
servers, more and more effort is being invested into defending against various kinds of …

Techniques for use in accordance with application performance decomposition are provided
which take advantage of the communications protocol used to carry a transaction between …

This paper advocates that cache coherence protocols use a bandwidth adaptive approach
to adjust to varied system configurations (eg, number of processors) and workload …

With transistor miniaturization leading to an abundance of on-chip resources and
uniprocessor designs providing diminishing returns, the industry has moved beyond single …

Recent work has argued that sequential consistency (SC) in GPUs can perform on par with
weak memory models, provided ordering stalls are made less frequent by relaxing ordering …

Future many-core CMP designs that will integrate tens of processor cores on-chip will be
constrained by area and power. Area constraints make impractical the use of a bus or a …

A new memory coherence protocol, Tardis, is proposed. Tardis uses timestamp counters
representing logical time as well as physical time to order memory operations and enforce …

Cache coherence has been studied extensively in the context of chip multiprocessors
(CMP). It is well known that conventional directory-based and snooping coherence protocols …

Recent work has shown that silent stores--stores which write a value matching the one
already stored at the memory location--occur quite frequently and can be exploited to reduce …

In this paper, we present a detailed characterization of the memory system, behavior of
ECperf and SPECjbb using both commercial server hardware and Simics full-system …