In this paper, we survey the application of linear network coding to a multiple unicasts
scenario in directed graphs. We discuss related work concerning the complexity of the …

Multi-core architectures also referred to as Chip Multiprocessors (CMPs) have emerged as
the dominant architecture for both desktop and high-performance systems. CMPs introduce …

In multicore systems, the concurrent access to shared data generates a bottleneck for the
system performance. Cache coherence techniques have been introduced to enable fast …

In symmetric multiprocessors (SMPs), the cache coherence overhead and the speed of the
shared buses limit the address/snoop bandwidth needed to broadcast transactions to all …

Location-based services for mobile devices are pervasive, and frequently process data
sensed from nearby devices as relevance is often dependent on proximity. Yet, today's …

In many-core CMP architectures, the cache coherence protocol is a key component since it
can add requirements of area and power consumption to the final design and, therefore, it …

Automotive connectivity standards promise to usher in new apps and services that utilize
vehicle-to-vehicle communications, and mobile app trends point to the potential of direct …

There are two important hurdles that restrict the scalability of directory-based shared-
memory multiprocessors: the directory memory overhead and the long L2 miss latencies due …

Shared memory is the predominant programming model in today's MPSoCs. However,
existing SoC on-chip communication standards like AMBA relies on the interconnect for …

We describe MESIF, a new cache coherence protocol. Based on point-to-point
communication links, the protocol maintains no directory, and mimics the broadcast behavior …