We address the primary limitation of the bandwidth to satisfy the demands for address
transactions in future cache-coherent symmetric multiprocessors (SMPs). It is widely known …

Higher integration lowers total cost of ownership (TCO) in the data center by reducing
equipment cost and lowering energy consumption. However, higher integration also makes …

Cache memory is a main component of memory hierarchy which plays an important role in
the overall performance of the system and in the design of multicores. Multicores with shared …

Traditional directory-based cache coherence protocols suffer from long-latency cache
misses as a consequence of the indirection introduced by the home node, which must be …

A new memory coherence protocol, Tardis, is proposed. Tardis uses timestamp counters
representing logical time as well as physical time to order memory operations and enforce …

This thesis focuses on mechanisms that improve inter-processor communication in
hardware shared-memory multiprocessors by detecting and exploiting knowledge of the …

Traditionally, cache coherence in large-scale shared-memory multiprocessors has been
ensured by means of a distributed directory structure stored in main memory. In this way, the …

Data access in modern processors contributes significantly to the overall performance and
energy consumption. Traditionally, data is distributed among the cores through an on-chip …

This thesis is motivated by the growing differential between main memory and
microprocessor core performance. Increased integration, enabled by Moore's law, has …

The infrastructure to support electronic commerce is one of the areas where more
processing power is needed. A multiprocessor system can offer advantages for running …