Hybrid coherence protocols can provide the scalability of directory protocols and low latency
sharing miss handling in snooping protocols simultaneously. Unfortunately, how to adapt the …

Networks-on-chip (NoCs) are key components in many-core chip designs. Dynamic power-
awareness is a new challenge present in NoCs that must be efficiently handled by the …

Cache coherence is one of the main challenges to tackle when designing a shared-memory
multiprocessors system. Incoherence may happen when multiple actors in a system are …

The semiconductor industry is experiencing a shift from “computation-bound design” to
“communication-bound design.” Many future systems will use one or many chip …

In many fields including digital image processing and artificial retina design, they always
confront a balance issue among real-time, accuracy, computing load, power consumption …

Future shared-memory multiprocessor servers will target commercial workloads using highly-
integrated “glueless" designs. Commercial workloads, which exhibit frequent sharing …

Energy-Efficient and High-Performance Nanophotonic Interconnects for Shared Memory
Multicores A dissertation presented to the fa Page 1 Energy-Efficient and High-Performance …

In glueless shared-memory multiprocessors where cache coherence is usually maintained
using a directory-based protocol, the fast access to the on-chip components (caches and …

Recent computer architecture trends herald the arrival of massive multiprocessors with more
than a hundred processor cores within a single package. In this setting, on-chip …

Abstract The Graphics Processing Unit (GPU) has become a mainstream computing platform
for a wide range of applications. Unlike latency-critical Central Processing Units (CPUs) …