A Formal Framework for Designing Verifiable Protocols

O Matthews - 2017 - search.proquest.com
Protocols play critical roles in computer systems today, including managing resources,
facilitating communication, and coordinating actions of components. It is highly desirable to …

[PDF][PDF] SOLVING THE MYSTERY OF TRANSFERRED OF CACHED DATA IN A MULTIPROCESSOR, OLTP ENVIRONMENT

B Kwait, K Shaw - dreuarchive.cra.org
Commercial databases run on multiprocessor systems exhibit particularly high levels of false
data sharing resulting from the low cache coherency present in such systems. These …

[PDF][PDF] CHAMPP: CHalmers Adaptable Multicore Processing Project

P Larsson-Edefors, SA McKee, P Stenström… - wiki.portal.chalmers.se
Performance growth of single processor systems recently stalled because of power and heat
problems associated with increasing the clock frequency. In order to continue to deliver a …

[PDF][PDF] SCORPIO: 36-Core Shared-Memory Processor Demonstrating Snoopy Coherence on a Mesh Interconnect

BK Daya, CHO Chen, S Subramanian, WC Kwon… - scorpio.mit.edu
Existing shared-memory multicore processors utilizing snoopy coherence, explicitly require
ordering of requests to maintain memory consistency semantics. Unfortunately ordered …

Improving GPU programming models through hardware cache coherence

I Singh - 2013 - open.library.ubc.ca
Abstract Graphics Processing Units (GPUs) have been shown to be effective at achieving
large speedups over contemporary chip multiprocessors (CMPs) on massively parallel …

Caché de directorio multinivel escalable para CMP NUCAs

JJ Valls Mompó - 2012 - riunet.upv.es
El propósito de este proyecto es diseñar y evaluar por medio de simulación una nueva
estructura de directorio más escalable que los esquemas de caché de directorio …

Distributed Lock Using Timestamps

AU Shankar, AU Shankar - Distributed Programming: Theory and Practice, 2013 - Springer
This chapter presents a distributed program that implements the distributed lock service in
Chap. 11 over a fifo channel. It first solves a “distributed request scheduling” problem using …

[PDF][PDF] SIMD based multicore processor for image and video processing

X He - 2012 - waseda.repo.nii.ac.jp
Continuous improvements in image and video processing require high computational power
to deal with the increasing complexity of algorithms and higher definition video. Meanwhile …

[PDF][PDF] Mobile Home Node: Improving Directory Cache Coherence Performance in NoCs via Exploitation of Producer-Consumer Relationships

T Soni - 2011 - oaktrust.library.tamu.edu
The implementation of multiple processors on a single chip has been made possible with
advancements in process technology. The benefits of having multiple cores on a single chip …

[PS][PS] Levo: A Resource-Flow Computer

AK Uht, D Morano, A Khala, M de Alba, S Langford… - ece.neu.edu
A number of limit studies have concluded that there exists a large amount of Instruction
Level Parallelism (ILP factors of 10 or more) in typical integer codes (eg, SPEC). However …