The road for 2D semiconductors in the silicon age

S Wang, X Liu, P Zhou - Advanced Materials, 2022 - Wiley Online Library
Continued reduction in transistor size can improve the performance of silicon integrated
circuits (ICs). However, as Moore's law approaches physical limits, high‐performance …

A survey on processing-in-memory techniques: Advances and challenges

K Asifuzzaman, NR Miniskar, AR Young, F Liu… - … , Devices, Circuits and …, 2023 - Elsevier
Abstract Processing-in-memory (PIM) techniques have gained much attention from computer
architecture researchers, and significant research effort has been invested in exploring and …

Breaking the von Neumann bottleneck: architecture-level processing-in-memory technology

X Zou, S Xu, X Chen, L Yan, Y Han - Science China Information Sciences, 2021 - Springer
The “memory wall” problem or so-called von Neumann bottleneck limits the efficiency of
conventional computer architectures, which move data from memory to CPU for …

FPGA-based near-memory acceleration of modern data-intensive applications

G Singh, M Alser, DS Cali, D Diamantopoulos… - IEEE Micro, 2021 - ieeexplore.ieee.org
Modern data-intensive applications demand high computational capabilities with strict
power constraints. Unfortunately, such applications suffer from a significant waste of both …

Syncron: Efficient synchronization support for near-data-processing architectures

C Giannoula, N Vijaykumar… - … Symposium on High …, 2021 - ieeexplore.ieee.org
Near-Data-Processing (NDP) architectures present a promising way to alleviate data
movement costs and can provide significant performance and energy benefits to parallel …

Van der Waals ferroelectric semiconductor field effect transistor for in-memory computing

J Liao, W Wen, J Wu, Y Zhou, S Hussain, H Hu, J Li… - ACS …, 2023 - ACS Publications
In-memory computing is a highly efficient approach for breaking the bottleneck of von
Neumann architectures, ie, reducing redundant latency and energy consumption during the …

NERO: A near high-bandwidth memory stencil accelerator for weather prediction modeling

G Singh, D Diamantopoulos… - … Conference on Field …, 2020 - ieeexplore.ieee.org
Ongoing climate change calls for fast and accurate weather and climate modeling. However,
when solving large-scale weather prediction simulations, state-of-the-art CPU and GPU …

A survey of domain-specific architectures for reinforcement learning

M Rothmann, M Porrmann - IEEE Access, 2022 - ieeexplore.ieee.org
Reinforcement learning algorithms have been very successful at solving sequential decision-
making problems in many different problem domains. However, their training is often time …

Multiply accumulate operations in memristor crossbar arrays for analog computing

J Chen, J Li, Y Li, X Miao - Journal of Semiconductors, 2021 - iopscience.iop.org
Memristors are now becoming a prominent candidate to serve as the building blocks of non-
von Neumann in-memory computing architectures. By mapping analog numerical matrices …

An introduction to the compute express link (cxl) interconnect

DD Sharma, R Blankenship, DS Berger - arXiv preprint arXiv:2306.11227, 2023 - arxiv.org
The Compute Express Link (CXL) is an open industry-standard interconnect between
processors and devices such as accelerators, memory buffers, smart network interfaces …