As the number of cores per die increases, be they processors, memory blocks, or custom
accelerators, the on-chip interconnect the cores use to communicate gains importance. We …

Today's scalable high-performance applications heavily depend on the bandwidth
characteristics of their communication patterns. Contemporary multi-stage interconnection …

Historically, processor accesses to memory-mapped device registers have been marked
uncachable to insure their visibility to the device. The ubiquity of snooping cache coherence …

In this paper we present and analyze a number of interconnect architectures for
reconfigurable systems targeting applications in the areas of wireless communication and …

Compressionless routing (CR) is an adaptive routing framework which provides a unified
framework for efficient deadlock free adaptive routing and fault tolerance. CR exploits the …

Most recent MPP systems employ a fast microprocessor surrounded by a shell of
communication and synchronization logic. The CRAY-T3D provides an elaborate shell to …

In today's multicomputers, software overhead dominates the message-passing latency cost.
We designed two multicomputer network interfaces that significantly reduce this overhead …

As modern computing systems become increasingly complex, communication efficiency
among and inside chips has become as important as the computation speeds of individual …

A family of oblivious routing schemes for fat trees and their slimmed versions is presented in
this work. First, two popular oblivious routing algorithms, which we refer to as S-mod-k and D …

This paper considers the ultimate impact of fundamental physical limitations-notably, speed
of light and device size-on parallel computing machines. Although we fully expect an …