[PDF][PDF] Design and simulation of ring network-on-chip for different configured nodes
A Jain, RK Dwivedi, H Alshazly, A Kumar… - … Materials & Continua, 2022 - cdn.techscience.cn
The network-on-chip (NoC) technology is frequently referred to as a front-end solution to a
back-end problem. The physical substructure that transfers data on the chip and ensures the …
back-end problem. The physical substructure that transfers data on the chip and ensures the …
Design automation for application-specific on-chip interconnects: A survey
On-chip interconnects provide a vital facility for highly parallel MultiProcessor Systems-on-
Chip, particularly in data-intensive applications, where the choice of the underlying …
Chip, particularly in data-intensive applications, where the choice of the underlying …
Mathematical formalisms for performance evaluation of networks-on-chip
This article reviews four popular mathematical formalisms—queueing theory, network
calculus, schedulability analysis, and dataflow analysis—and how they have been applied …
calculus, schedulability analysis, and dataflow analysis—and how they have been applied …
An analytical latency model for networks-on-chip
We propose an analytical model based on queueing theory for delay analysis in a wormhole-
switched network-on-chip (NoC). The proposed model takes as input an application …
switched network-on-chip (NoC). The proposed model takes as input an application …
Multicasting mesh AER: A scalable assembly approach for reconfigurable neuromorphic structured AER systems. Application to ConvNets
C Zamarreño-Ramos… - IEEE transactions on …, 2012 - ieeexplore.ieee.org
This paper presents a modular, scalable approach to assembling hierarchically structured
neuromorphic Address Event Representation (AER) systems. The method consists of …
neuromorphic Address Event Representation (AER) systems. The method consists of …
Impact of on-chip interconnect on in-memory acceleration of deep neural networks
With the widespread use of Deep Neural Networks (DNNs), machine learning algorithms
have evolved in two diverse directions—one with ever-increasing connection density for …
have evolved in two diverse directions—one with ever-increasing connection density for …
Performance analysis of network-on-chip in many-core processors
AV Bhaskar, TG Venkatesh - Journal of Parallel and Distributed Computing, 2021 - Elsevier
Abstract Network-on-chip (NoC) is an integral part of many-core microprocessors.
Performance analysis of network-on-chip directly affects the performance of the …
Performance analysis of network-on-chip directly affects the performance of the …
Path-congestion-aware adaptive routing with a contention prediction scheme for network-on-chip systems
Network-on-chip systems can achieve higher performance than bus systems for chip
multiprocessor systems. However, as the complexity of the network increases, the channel …
multiprocessor systems. However, as the complexity of the network increases, the channel …
Mathematical modeling and control of multifractal workloads for data-center-on-a-chip optimization
P Bogdan - Proceedings of the 9th International Symposium on …, 2015 - dl.acm.org
Building autonomous data-centers-on-chip (DCoC) for exascale computing requires
mathematical frameworks that account and exploit the non-stationary and multi-fractal …
mathematical frameworks that account and exploit the non-stationary and multi-fractal …
A support vector regression (SVR)-based latency model for network-on-chip (NoC) architectures
In this paper, we propose SVR-NoC, a network-on-chip (NoC) latency model using support
vector regression (SVR). More specifically, based on the application communication …
vector regression (SVR). More specifically, based on the application communication …