Energy efficient and high performance 64-bit Arithmetic Logic Unit using 28nm technology

S Murgai, A Gupta… - … Conference on Advances …, 2015 - ieeexplore.ieee.org
Arithmetic Logic Units are one of the vital unit in general purpose processors and major
source of power dissipation. In this paper we have demonstrated an optimized Arithmetic …

Design and implementation of power efficient clock gated dual-port SRAM

MW Bhat, R Kaartik, KB Sowmya - Journal of Physics …, 2022 - iopscience.iop.org
Synchronous clock gated Dual-port RAM has been designed in this paper. To increase the
design's power, a negative latch-based clock gating approach was used. On Xilinx Vivado …

Power efficient, clock gated multiplexer based full adder cell using 28 nm technology

A Gupta, S Murgai, A Gulati, P Kumar - AIP Conference Proceedings, 2016 - pubs.aip.org
ClocN gating is a leading technique used for power saving. Full adders is one of the basic
circuit that can be found in maximum VLSI circuits. In this paper clocN gated multiplexer …

Design and implementation of low power clock gated 64-bit ALU on ultra scale FPGA

A Gupta, S Murgai, A Gulati, P Kumar - AIP Conference Proceedings, 2016 - pubs.aip.org
64-bit energy efficient Arithmetic and Logic Unit using negative latch based clocN gating
technique is designed in this paper. The 64-bit ALU is designed using multiplexer based full …

Design and implementation of power efficient 10-bit dual port SRAM on 28 nm technology

A Gulati, A Gupta, S Murgai, L Bhaskar - AIP Conference Proceedings, 2016 - pubs.aip.org
In this paper, 10 bit synchronous clock gated Dual port RAM has been designed. The
negative latch based clock gating technique has been employed to optimize the power of …

Design and Implementation of Floating Point Sine and Cosine Functions Using Xilinx ISE for Analog Circuits.

M Duhan - IUP Journal of Electrical & Electronics …, 2018 - search.ebscohost.com
The paper performs the design and implementation of sine and cosine functions in floating
point format. To implement these functions, an iterative shift-add algorithm called Co …

[PDF][PDF] Design And Implementation Of Sine And Cosine Generator Using CORDIC Hardware In VHDL

KRN Gaonkar, S Kuwelkar - scholar.archive.org
Many Digital signal processing application s are based on real time constraints. Therefore,
conventional processors are not suitable for modern day DSP systems, leading major issues …