Efficient implementations of 4-bit burst error correction for memories

J Li, L Xiao, P Reviriego… - IEEE Transactions on …, 2018 - ieeexplore.ieee.org
In recent years, there has been a growing interest in error correction codes (ECCs) that can
correct localized errors in memories. This is due to the larger fraction of radiation induced …

Ultrafast codes for multiple adjacent error correction and double error detection

LJ Saiz-Adalid, J Gracia-Moran, D Gil-Tomas… - IEEE …, 2019 - ieeexplore.ieee.org
Reliable computer systems employ error control codes (ECCs) to protect information from
errors. For example, memories are frequently protected using single error correction-double …

Compact and power efficient SEC-DED codec for computer memory

J Samanta, J Bhaumik, S Barman - Microsystem Technologies, 2021 - Springer
Frequently, soft errors occur due to striking of radioactive particles in memory cells which
reduce the reliability of memory systems. Generally, single error correction-double error …

Low delay single error correction and double adjacent error correction (SEC-DAEC) codes

J Li, P Reviriego, L Xiao, Z Liu, L Li, A Ullah - Microelectronics Reliability, 2019 - Elsevier
In recent years, there has been a growing interest in codes that can correct adjacent bit
errors in memories. This is due to the increasing percentage of radiation induced errors that …

Construction of cyclic redundancy check codes for SDDC decoding in DRAM systems

J Kim, S Kwon, J Noh, DJ Shin - IEEE Transactions on Circuits …, 2022 - ieeexplore.ieee.org
Single device data correction (SDDC) is a main reliability, availability, and serviceability
feature of DRAM systems in servers due to the significant hard-failure rate associated with …

A single and adjacent error correction code for fast decoding of critical bits

K Namba, F Lombardi - IEEE Transactions on Computers, 2018 - ieeexplore.ieee.org
Many systems have critical bits which must be decoded at high speeds; for example, flags to
mark the start and end of a packet (SOP and EOP) determine subsequent actions, thus they …

Semiconductor device including error correction code unit that generates data block matrix including plural parity blocks and plural data block groups diagonally …

DS Kim, CS Chae - US Patent 10,700,712, 2020 - Google Patents
A semiconductor device includes a controller and a memory device. The controller includes
a processor configured to process a request from an external apparatus, an interface …

Efficient concurrent error detection for SEC-DAEC encoders

J Li, P Reviriego, C Argyrides… - 2019 IEEE 25th …, 2019 - ieeexplore.ieee.org
In the last decade, a number of Single Error Correction Double Adjacent Error Correction
(SEC-DAEC) codes have been proposed to protect memories against Multiple Cell Upsets …

An Approach to Reduce Power Consumption and Delay of Single Error Correction Codes in WSNs for IoT Applications

J Jana, S Tripathi, J Samanta, J Bhaumik… - Computers and Devices …, 2021 - Springer
Single error correction (SEC) codes have been employed to protect the data bits as well as
control bits in wireless sensor networks (WSNs) for Internet of Things (IoT) applications. In …

A Fast Technique to Reduce Power Consumption on Linear Block Codes Used to Protect Registers

R González-Toral, P Reviriego… - … on Device and …, 2018 - ieeexplore.ieee.org
In recent years, both radiation induced faults and power consumption have become
important factors to consider when designing circuits for space applications. These faults …