Strained Si0.2Ge0.8/Ge multilayer Stacks Epitaxially Grown on a Low-/High-Temperature Ge Buffer Layer and Selective Wet-Etching of Germanium
With the development of new designs and materials for nano-scale transistors, vertical Gate-
All-Around Field Effect Transistors (vGAAFETs) with germanium as channel materials have …
All-Around Field Effect Transistors (vGAAFETs) with germanium as channel materials have …
Diffusion mechanism of fluorine in plasma processing of III–V semiconductor compounds
Y Kodama, Y Zaizen, H Minari, Y Cho… - Japanese Journal of …, 2020 - iopscience.iop.org
III–V semiconductors have attracted attention as high mobility channel materials in
advanced metal oxide semiconductors. However, there is a possibility that their …
advanced metal oxide semiconductors. However, there is a possibility that their …
Low damage patterning of In0. 53Ga0. 47As film for its integration as n-channel in a fin metal oxide semiconductor field effect transistor architecture
M Bizouerne, E Pargon, C Petit-Etienne… - Journal of Vacuum …, 2018 - pubs.aip.org
One of the challenges of InGaAs integration as a channel in a fin field effect transistor
architecture is the patterning of the III–V fin with nanometer scale definition, vertical …
architecture is the patterning of the III–V fin with nanometer scale definition, vertical …
Sub-10 nm plasma nanopatterning of InGaAs with nearly vertical and smooth sidewalls for advanced n-fin field effect transistors on silicon
This work focuses on the nanopatterning of sub-10 nm InGaAs fins by inductively coupled
plasma reactive ion etching for advanced III− V n-fin field effect transistors (n-FinFETs) on …
plasma reactive ion etching for advanced III− V n-fin field effect transistors (n-FinFETs) on …
High Aspect Ratio Junctionless InGaAs FinFETs Fabricated Using a Top-Down Approach
DAJ Millar, X Li, U Peralagu, MJ Steer… - 2018 76th Device …, 2018 - ieeexplore.ieee.org
The junctionless MOSFET (JLFET) architecture has attracted much attention as an enabling
technology for ultra-scaled CMOS devices [1]. The dominant scattering mechanism in …
technology for ultra-scaled CMOS devices [1]. The dominant scattering mechanism in …
Développement de procédés de gravure plasma sans dommages pour l'intégration de l'InGaAs comme canal tridimensionnel de transistor nMOS non-planaire
M Bizouerne - 2018 - theses.hal.science
L'augmentation des performances des dispositifs de la microélectronique repose encore
pour une dizaine d'années sur une miniaturisation des circuits intégrés. Cette …
pour une dizaine d'années sur une miniaturisation des circuits intégrés. Cette …