A variable threshold voltage inverter for CMOS programmable logic circuits

J Segura, JL Rosselló, J Morra… - IEEE Journal of Solid …, 1998 - ieeexplore.ieee.org
A programmable input threshold voltage inverter compatible with double gate transistors
fabrication processes is presented. Such a circuit is useful as a programmable input …

Ultrafast large-scale chemical sensing with CMOS ISFETs: A level-crossing time-domain approach

Y Liu, TG Constandinou… - IEEE Transactions on …, 2019 - ieeexplore.ieee.org
The introduction of large-scale chemical sensing systems in CMOS which integrate millions
of ISFET sensors have allowed applications such as DNA sequencing and fine-pixel …

Analytical transient response and propagation delay model for nanoscale CMOS inverter

Y Wang, M Zwolinski - 2009 IEEE International Symposium on …, 2009 - ieeexplore.ieee.org
This paper presents a new analytical propagation delay model for nanoscale CMOS
inverters. By using a non-saturation current model, the analytical input-output transfer …

Signal transition time effect on CMOS delay evaluation

D Auvergne, JM Daga… - IEEE Transactions on …, 2000 - ieeexplore.ieee.org
Realistic modeling of gate delay is of great importance in evaluating circuit path
performances. Nonzero signal rise and fall times contribute to gate propagation delays and …

An analytical charge-based compact delay model for submicrometer CMOS inverters

JL Rosselló, J Segura - … Transactions on Circuits and Systems I …, 2004 - ieeexplore.ieee.org
We develop an accurate analytical expression for the propagation delay of submicrometer
CMOS inverters that takes into account the short-circuit current, the input-output coupling …

Transition time modeling in deep submicron CMOS

P Maurine, M Rezzoug, N Azemard… - IEEE Transactions on …, 2002 - ieeexplore.ieee.org
As generally recognized, the performance of a CMOS gate, such as propagation delay time
or short circuit power dissipation, is strongly affected by the nonzero input signal transition …

[图书][B] Logic-timing simulation and the degradation delay model

MJ Bellido, JJ Chico, M Valencia - 2006 - books.google.com
This book provides the reader with an extensive background in the field of logic-timing
simulation and delay modeling. It includes detailed information on the challenges of logic …

Impact of microwave interference on dynamic operation and power dissipation of CMOS inverters

K Kim, AA Iliadis - IEEE transactions on electromagnetic …, 2007 - ieeexplore.ieee.org
The effects of electromagnetic interference (EMI) from high-power microwave signals on
CMOS inverters are reported. In order to study these effects more effectively, a novel …

[PDF][PDF] Comparative study for delay & power dissipation of CMOS Inverter in UDSM range

J Samanta, BP De, B Bag, RK Maity - International Journal of Soft …, 2012 - academia.edu
Delay and power are two major issues in design and synthesis of VLSI circuits which
depends on different design parameters. In this paper, the relative study of propagation …

Delay and current estimation in a CMOS inverter with an RC load

M Hafed, M Oulmane, NC Rumin - IEEE Transactions on …, 2001 - ieeexplore.ieee.org
A novel and efficient method is presented for computing the delay and supply current pulse
in a CMOS inverter with an RC load. The method builds on existing techniques for …