The authors present the Inertial and Degradation Delay Model (IDDM) for CMOS digital
simulation. The model combines the degradation delay model presented in previous papers …

This paper presents a technique for the modeling and design of a nano scale CMOS inverter
circuit using artificial neural network and particle swarm optimization algorithm such that the …

Non zero signal rise and fall times contribute significantly to CMOS gate performances such
as propagation delay or short circuit power dissipation. We present a closed form expression …

This contribution extends the Degradation Delay Model (DDM), previously developed for
CMOS inverters, to simple logic gates. A gate-level approach is followed. At a first stage, all …

In previous papers we have presented a very accurate model that handles the generation
and propagation of glitches, which makes an important headway in logic timing simulation …

Microwave or electromagnetic interference (EMI) can couple into electronic circuits and
systems intentionally from high power microwave (HPM) sources or unintentionally due to …

Negative Bias Temperature Instability (NBTI) has become an important cause of degradation
in scaled PMOS devices, affecting power, performance, yield and reliability of circuits. This …

This paper presents HALOTIS, a novel high accuracy logic timing simulation tool, that
incorporates a new simulation algorithm based on different concepts for transitions and …

Gaussian pulse is widely used in communication systems. The true Gaussian function is not
physically realizable, but it can be approximated through linear functions. This paper …

In this paper the dynamic behavior of series-connected MOSFETs is studied, in order to
compute the propagation delay of multiple-input static CMOS gates. A method for the …