Analytical methods for gate delay estimation are very useful to speedup timing analysis of
digital integrated circuits. This work presents a novel approach to analytically estimate the …

With shrinking transistor dimensions into sub-50-nm regime, statistical variability (SV)
causes a great impact on the drain current and threshold voltage of nano-MOSFETs. In this …

The primary goal of this research paper is to examine the impact of different design
parameters on the power-delay product (PDP) in low-power very-large-scale integration …

Pass transistor logic has become important for the design of low‐power high‐performance
digital circuits due to the smaller node capacitances and reduced transistors count it offers …

In this paper, a piecewise linear delay model which can predict the accurate propagation
delay of the general CMOS VLSI circuitry is presented. The model takes into account the …

Current literature provides many practical tools or theoretical methods to plan and
dimension GSM or UMTS radio networks but overlooks the algorithms of network plan and …

In this paper, we have developed a simple and accurate delay model for any Ultra Deep Sub-
micron (UDSM) CMOS inverter, NAND2 & NOR2 based on n th power law of MOSFET …

The art of ERP implementation stands in matching ERP features with the requirements of an
organisation so as to define how to adapt the system and/or the organisation to reach a …

A method for collapsing the transistor chain of CMOS gates to a single equivalent transistor
is introduced. The width of the equivalent transistor is calculated taking into account the …

This paper introduces a numerical method for time domain analysis of the inverter driving
interconnect in CMOS digital integrated circuits. To include the carriers' velocity saturation …