The scaling challenge: can correct-by-construction design help?
P Saxena, N Menezes, P Cocchini… - Proceedings of the 2003 …, 2003 - dl.acm.org
We present the results of scaling studies in the context of typical block-level wiring
distributions, and study the impact of the identified trends on the post-RTL design process. In …
distributions, and study the impact of the identified trends on the post-RTL design process. In …
Dynamic clock management for low power applications in FPGAs
I Brynjolfson, Z Zilic - Proceedings of the IEEE 2000 Custom …, 2000 - ieeexplore.ieee.org
Low power techniques employing dynamically controlled clock rates offer potentially
powerful energy saving capabilities. In this paper, we consider the application of this low …
powerful energy saving capabilities. In this paper, we consider the application of this low …
GALS implementation of randomly prioritized buffer-less routing architecture for 3D NoC
A Karthikeyan, PS Kumar - Cluster Computing, 2018 - Springer
Recently, there has been enormous attention given to the network on chip (NoC) because it
is scalable compared to the communication bus. Three dimensional (3D) NoC is getting …
is scalable compared to the communication bus. Three dimensional (3D) NoC is getting …
Embedding universal delay-insensitive circuits in asynchronous cellular spaces
Abstract Asynchronous Cellular Automata (ACA) are cellular automata which allow cells to
be updated at times that are random and independent of each other. Due to their …
be updated at times that are random and independent of each other. Due to their …
DICE-based Muller C-elements for soft error tolerant asynchronous ICs
IA Danilov, MS Gorbunov, AI Shnaider… - 2016 16th European …, 2016 - ieeexplore.ieee.org
Muller C-element is one of the main parts of an asynchronous circuit. Being sequential by its
nature, it is vulnerable to single event upsets (SEU). We propose three 65 nm CMOS circuit …
nature, it is vulnerable to single event upsets (SEU). We propose three 65 nm CMOS circuit …
Minimum-energy sub-threshold self-timed circuits: design methodology and a case study
This paper addresses the design of self-timed energy-minimum circuits, operating in the sub-
VT domain. The paper presents a generic implementation template using bundled-data …
VT domain. The paper presents a generic implementation template using bundled-data …
Dali: A gridded cell placement flow
Asynchronous Very-Large-Scale-Integration (VLSI) has several potential benefits over its
synchronous counterparts, such as reduced power consumption, elastic pipelining, and …
synchronous counterparts, such as reduced power consumption, elastic pipelining, and …
BCS superfluidity in ultracold gases with unequal atomic populations
R Combescot - Europhysics Letters, 2001 - iopscience.iop.org
We consider the existence of a BCS superfluid phase in 6 Li due to the pairing of two
hyperfine states with unequal number of atoms. We show that the domain of existence for …
hyperfine states with unequal number of atoms. We show that the domain of existence for …
Globally asynchronous locally synchronous architecture for large high-performance ASICs
Clock nets are the major source of power consumption in large, high-performance ASICs
and a design bottleneck when it comes to tolerable clock skew. A way to obviate the global …
and a design bottleneck when it comes to tolerable clock skew. A way to obviate the global …