An asynchronous cellular automaton implementing 2-state 2-input 2-output reversed-twin reversible elements

J Lee, F Peper, S Adachi, K Morita - … on Cellular Aotomata for Reseach and …, 2008 - Springer
Reversible computers usually work in a synchronous mode, ie, in the presence of clock
signals, but in the light of the asynchronous nature of microscopic physical phenomena this …

Self-timed cellular automata and their computational ability

F Peper, T Isokawa, N Kouda, N Matsui - Future Generation Computer …, 2002 - Elsevier
This paper describes a novel type of Asynchronous Cellular Automata, in which transitions
of cells only take place when triggered by transitions of their neighboring cells. Called Self …

Fault-tolerant distributed clock generation in VLSI systems-on-chip

M Fugger, U Schmid, G Fuchs… - 2006 Sixth European …, 2006 - ieeexplore.ieee.org
This paper introduces a simple fault-tolerant tick generation algorithm based on Srikanth &
Toueg's consistent broadcast primitive that can be directly implemented in VLSI using …

Elliptic curve cryptosystems on reconfigurable hardware

MC Rosner - 1999 - digital.wpi.edu
Security issues will play an important role in the majority of communication and computer
networks of the future. As the Internet becomes more and more accessible to the public …

On board electronic devices safety provided by DICE-based Muller C-elements

IA Danilov, MS Gorbunov, AI Shnaider, AO Balbekov… - Acta Astronautica, 2018 - Elsevier
Abstract Space radiation interacting with electronic components of on-board computing or
navigation unit can bring to it's malfunction. Using error tolerant electronic components is a …

Asynchronous circuit design: Motivation, background, & methods

A Davis, SM Nowick - Asynchronous Digital Circuit Design, 1995 - Springer
The purpose of this book is to present a current view of the state of the art for the field of
asynchronous circuit design and analysis which was the topic of a workshop in Banff in the …

Robust corrective control against fundamental and non-fundamental mode attacks with application to an asynchronous digital system

JM Yang, SW Kwak - Information Sciences, 2024 - Elsevier
This article presents a robust model matching corrective control scheme for input/state
asynchronous sequential machines (ASMs) vulnerable to both fundamental and non …

Performance analysis of latency-insensitive systems

R Lu, CK Koh - IEEE Transactions on Computer-Aided Design …, 2006 - ieeexplore.ieee.org
This paper formally models and studies latency-insensitive systems (LISs) through max-plus
algebra. We introduce state traces to model behaviors of LISs and obtain a formally proved …

A new asynchronous pipeline scheme: application to the design of a self-timed ring divider

M Renaudin, BE Hassan… - IEEE Journal of Solid-State …, 1996 - ieeexplore.ieee.org
This paper describes an efficient means of synchronizing and pipelining asynchronous
circuits implemented using differential cascode voltage switch logic (DCVSL) precharged …

[图书][B] Asynchronous pulse logic

M Nyström - 2001 - search.proquest.com
This thesis explores a new way of computing with CMOS digital circuits, single-track-
handshake asynchronous pulse-logic (STAPL). These circuits are similar to quasi delay …