RM Al Sheikh, S Priyadarshi, B Dwiel… - US Patent …, 2019 - Google Patents
A first load instruction specifying a first virtual address misses in a data cache. A delta value is received based on a program counter value of the first load instruction. A second virtual …
L Xu, W Pu, R Ramanath, K Liu - US Patent 10,346,304, 2019 - Google Patents
Techniques related to cache management for multi-node databases are disclosed. In some embodiments, a system comprises one or more computing devices including a training …
Aspects disclosed in the detailed description include providing load address predictions using address prediction tables based on load path history in processor-based systems. In …