Predicting architectural vulnerability on multithreaded processors under resource contention and sharing

L Duan, L Peng, B Li - IEEE Transactions on Dependable and …, 2012 - ieeexplore.ieee.org
Architectural vulnerability factor (AVF) characterizes a processor's vulnerability to soft errors.
Interthread resource contention and sharing on a multithreaded processor (eg, SMT, CMP) …

Thread vulnerability in parallel applications

I Oz, HR Topcuoglu, M Kandemir, O Tosun - Journal of Parallel and …, 2012 - Elsevier
Continuously reducing transistor sizes and aggressive low power operating modes
employed by modern architectures tend to increase transient error rates. Concurrently …

Universal rules guided design parameter selection for soft error resilient processors

L Duan, Y Zhang, B Li, L Peng - (IEEE ISPASS) IEEE …, 2011 - ieeexplore.ieee.org
High-performance processors suffer from soft error vulnerability due to the increasing on-
chip transistor density, shrinking processor feature size, lower threshold voltage, etc. In this …

Comprehensive and efficient design parameter selection for soft error resilient processors via universal rules

L Duan, Y Zhang, B Li, L Peng - IEEE Transactions on …, 2013 - ieeexplore.ieee.org
Soft errors have been significantly degrading the reliability of current processors whose
feature sizes and supply voltages are fast scaling down. In this paper, we propose two …

Determining the vulnerability of multi-threaded program code to soft errors

V Sridharan, ME Wilkening, S Gurumurthi - US Patent 9,292,418, 2016 - Google Patents
The described embodiments include a program code testing system that determines the
vulnerability of multi-threaded program code to soft errors. For multi-threaded program code …

Reliability aware throughput management of chip multi-processor architecture via thread migration

F Pouyan, A Azarpeyvand, S Safari… - The Journal of …, 2016 - Springer
Integrating the large number of transistor in a single chip leads to significant improvement on
the performance of processors. More performance is achieved by putting multiple CPU cores …

Soft error mitigation techniques for future chip multiprocessors

GR Upasani - 2016 - upcommons.upc.edu
The sustained drive to downsize the transistors has reached a point where device sensitivity
against transient faults due to neutron and alpha particle strikes aka soft errors has moved to …

Examining thread vulnerability analysis using fault-injection

I Oz, HR Topcuoglu, M Kandemir… - 2013 IFIP/IEEE 21st …, 2013 - ieeexplore.ieee.org
With the scale down of transistor sizes and higher frequencies with low power modes in
modern architectures, the chip components become more susceptible to transient errors …

Reliability-aware core partitioning in chip multiprocessors

I Oz, HR Topcuoglu, M Kandemir, O Tosun - Journal of Systems …, 2012 - Elsevier
Executing multiple applications concurrently is an important way of utilizing the
computational power provided by emerging chip multiprocessor (CMP) architectures …

Reducing source load in bittorrent

B Sanderson, D Zappala - 2009 Proceedings of 18th …, 2009 - ieeexplore.ieee.org
One of the main goals of BitTorrent is to reduce load on Web servers by encouraging clients
to share content between themselves. However, BitTorrent's current design relies heavily on …