A modern primer on processing in memory
Modern computing systems are overwhelmingly designed to move data to computation. This
design choice goes directly against at least three key trends in computing that cause …
design choice goes directly against at least three key trends in computing that cause …
Uncovering in-dram rowhammer protection mechanisms: A new methodology, custom rowhammer patterns, and implications
The RowHammer vulnerability in DRAM is a critical threat to system security. To protect
against RowHammer, vendors commit to security-through-obscurity: modern DRAM chips …
against RowHammer, vendors commit to security-through-obscurity: modern DRAM chips …
DAMOV: A new methodology and benchmark suite for evaluating data movement bottlenecks
Data movement between the CPU and main memory is a first-order obstacle against improv
ing performance, scalability, and energy efficiency in modern systems. Computer systems …
ing performance, scalability, and energy efficiency in modern systems. Computer systems …
Blockhammer: Preventing rowhammer at low cost by blacklisting rapidly-accessed dram rows
Aggressive memory density scaling causes modern DRAM devices to suffer from
RowHammer, a phenomenon where rapidly activating (ie, hammering) a DRAM row can …
RowHammer, a phenomenon where rapidly activating (ie, hammering) a DRAM row can …
A deeper look into rowhammer's sensitivities: Experimental analysis of real dram chips and implications on future attacks and defenses
RowHammer is a circuit-level DRAM vulnerability where repeatedly accessing (ie,
hammering) a DRAM row can cause bit flips in physically nearby rows. The RowHammer …
hammering) a DRAM row can cause bit flips in physically nearby rows. The RowHammer …
Rega: Scalable rowhammer mitigation with refresh-generating activations
Mitigating Rowhammer requires performing additional refresh operations to recharge DRAM
rows before bits start to flip. These refreshes are scarce and can only happen periodically …
rows before bits start to flip. These refreshes are scarce and can only happen periodically …
Figaro: Improving system performance via fine-grained in-dram data relocation and caching
Main memory, composed of DRAM, is a performance bottleneck for many applications, due
to the high DRAM access latency. In-DRAM caches work to mitigate this latency by …
to the high DRAM access latency. In-DRAM caches work to mitigate this latency by …
Understanding RowHammer under reduced wordline voltage: An experimental study using real DRAM devices
RowHammer is a circuit-level DRAM vulnerability, where repeatedly activating and
precharging a DRAM row, and thus alternating the voltage of a row's wordline between low …
precharging a DRAM row, and thus alternating the voltage of a row's wordline between low …
Shadow: Preventing row hammer in dram with intra-subarray row shuffling
As Row Hammer (RH) attacks have been a critical threat to computer systems, numerous
hardware-based (HWbased) RH mitigation strategies have been proposed. However, the …
hardware-based (HWbased) RH mitigation strategies have been proposed. However, the …
PiDRAM: A Holistic End-to-end FPGA-based Framework for Processing-in-DRAM
Commodity DRAM-based processing-using-memory (PuM) techniques that are supported
by off-the-shelf DRAM chips present an opportunity for alleviating the data movement …
by off-the-shelf DRAM chips present an opportunity for alleviating the data movement …